參數(shù)資料
型號(hào)： AD9895
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processors with Precision Timing⑩ Generator
中文描述： CCD信號(hào)處理器，精確定時(shí)⑩發(fā)生器
文件頁數(shù)： 41/59頁
文件大?。?/td> 599K
代理商： AD9895
REV. A
AD9891/AD9895
–41–
SERIAL INTERFACE TIMING
All of the internal registers of the AD9891/AD9895 are accessed
through a 3-wire serial interface. Each register consists of a
10-bit address and a 6-bit data-word. Both the 10-bit address and
6-bit data-word are written starting with the LSB. To write to
each register, a 16-bit operation is required, as shown in
Figure 52. Although many registers are less than six bits wide, all
six bits must be written to for each register. If the register is only
two bits wide, then the upper four bits are Don
’
t Cares and can
be filled with 0s during the serial write operation. If less than six
bits are written, the register will not be updated with new data.
Because of the large number of registers in the AD9891/AD9895,
Figure 53 shows a more efficient way to write to the registers,
using the AD9891/AD9895
’
s address auto-increment capability.
Using this method, the lowest desired address is written first, fol-
lowed by multiple 6-bit data-words. Each new 6-bit data-word will
automatically be written to the next highest register address. By
eliminating the need for each 10-bit address to be written,
faster register loading is accomplished. Address auto-incre-
ment may be used starting with any register location and may be
used to write to as few as two registers or as many as the entire
register space.
Notes About Accessing a Double-Wide Register
There are many double-wide registers in the AD9891/
AD9895. These registers are configured into two consecutive
6-bit registers with the least significant six bits located in the
lower of the two addresses and the remaining most significant
bits located in the higher of the two addresses. For example, the
six LSBs of the OPRMODE Register, OPRMODE[5:0], are
located at Addr 0x00. The most significant six bits of the
OPRMODE Register, OPRMODE[11:6], are located at
Addr
0x1. The following rules must be followed when access-
ing
double-wide registers:
1. When accessing a double-wide register, BOTH addresses
must be written to.
2. The lower of the two consecutive addresses for the double-
wide register must be written to first. In the example of the
OPRMODE Register, the contents of Addr 0x00 must be
written first followed by the contents of Addr 0x01. The
register will be internally updated after the completion of
the write to Register 0x01, either at the next SL rising edge
or the next VD/HD falling edge depending on the register.
3. A single write to the lower of the two consecutive addresses
of a double-wide register that is not followed by a write to
the higher address of the registers is not supported. This will
not update the register.
4. A single write to the higher of the two consecutive addresses
of a double-wide register that is not preceded by a write to
the lower of the two addresses is not supported. Although
the write to the higher address will update the full double-
wide register, the lower six bits of the register will be written
with an indeterminate value if the lower address was not
written to first.
SDATA
A0
A1
A2
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
SCK
SL
A3
NOTES
SDATA BITS ARE LATCHED ON SCK RISING EDGES.
EACH INTERNAL REGISTER IS PRELOADED WITH NEW DATA AT SL RISING EDGE.
NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
t
DH
t
LS
t
LH
t
DS
VD
SL UPDATED
VD/HD UPDATED
HD
Figure 52. Serial Write Operation
SDATA
A0
A1
A2
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
A3
D0
D1
D2
D3
D4
D5
D0
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
SCK
SL
NOTES
MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS.
THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD.
SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 53. Continuous Serial Write Operation
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