參數(shù)資料
型號(hào)： AD9883AKSTZ-110
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大小： 0K
描述： IC FLAT PANEL INTERFACE 80-LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 顯示器，監(jiān)控器，電視
接口： 模擬
電源電壓： 3 V ~ 3.6 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
REV. B
AD9883A
–19–
0E
5
Hsync Output Polarity
This bit determines the polarity of the Hsync output and
the SOG output. Table XI shows the effect of this option.
SYNC indicates the logic state of the sync pulse.
Table XI. Hsync Output Polarity Settings
Setting
SYNC
0Logic 1 (Positive Polarity)
1Logic 0 (Negative Polarity)
The default setting for this register is 0.
0E
4
Active Hsync Override
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
Table XII. Active Hsync Override Settings
Override
Result
0Autodetermines the Active Interface
1
Override, Bit 3 Determines the Active Interface
The default for this register is 0.
0E
3
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Table XIII. Active HSYNC Select Settings
Select
Result
0HSYNC Input
1
Sync-on-Green Input
The default for this register is 0.
0E
2
Vsync Output Invert
This bit inverts the polarity of the Vsync output. Table
XIV shows the effect of this option.
Table XIV. Vsync Output Invert Settings
Setting
Vsync Output
0
Invert
1No Invert
The default setting for this register is 0.
0E
1 Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
Table XV. Active Vsync Override Settings
Override
Result
0Autodetermine the Active Vsync
1
Override, Bit 0 Determines the Active Vsync
The default for this register is 0.
0E
0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set (Bit 1).
Table XVI. Active Vsync Select Settings
Select
Result
0Vsync Input
1Sync Separator Output
The default for this register is 0.
0F
7 Clamp Input Signal Source
This bit determines the source of clamp timing.
Table XVII. Clamp Input Signal Source Settings
Clamp Function
Function
0Internally Generated Clamp Signal
1
Externally Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0FH, Bit 6).
The power-up default value is Clamp Function = 0.
0F
6 Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Table XVIII. Clamp Input Signal Polarity Settings
Clamp Function
Function
1Active Low
0Active High
A Logic 1 means that the circuit will clamp when CLAMP is
low, and it will pass the signal to the ADC when CLAMP is
high.
A Logic 0 means that the circuit will clamp when CLAMP
is high, and it will pass the signal to the ADC when
CLAMP is low.
The power-up default value is Clamp Polarity = 1.
0F
5 Coast Select
This bit is used to select the active Coast source. The
choices are the Coast Input Pin or Vsync. If Vsync is se-
lected the additional decision of using the Vsync input
pin or the output from the sync separator needs to be
made (Register 0E, Bits 1, 0).
Table XIX. Power-Down Settings
Select
Result
0Coast Input Pin
1Vsync (See above Text)
相關(guān)PDF資料
PDF描述
5227699-3 CONN JACK BNC STR 50 OHM PCB TIN
D38999/24WD19SA CONN RCPT 19POS JAM NUT W/SCKT
V150B24H150B CONVERTER MOD DC/DC 24V 150W
V150B12H150BG3 CONVERTER MOD DC/DC 12V 150W
V150B12H150BG CONVERTER MOD DC/DC 12V 150W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9883AKSTZ-110 制造商:Analog Devices 功能描述:IC ANALOG INTERFACE
AD9883AKSTZ-140 功能描述:IC FLAT PANEL INTERFACE 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD9883AKSTZ-RL110 功能描述:IC INTERFACE FLAT 110MHZ 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
AD9883KST-110 制造商:Rochester Electronics LLC 功能描述:110MHZ ANALOG INTERFACE F - Bulk
AD9884 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS Analog Flat Panel Interface
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*