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| 型號(hào)： | AD9865-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號(hào)前端 |
| 文件頁數(shù)： | 42/48頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | AD9865-EB |
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AD9865
Rev. A | Page 42 of 48
0
SAMPLE RATE (MSPS)
I
A
20
30
40
50
60
70
80
220
120
130
140
150
160
170
180
190
200
210
000
001
010
011
100
101
101 OR 111
Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate
0
SAMPLE RATE (MSPS)
S
T
20
80
60
70
30
40
50
61
51
–54
–74
–72
–70
–68
–66
–64
–62
–60
–58
–56
52
53
54
55
56
57
58
59
60
THD-000
THD-001
THD-010
THD-011
THD-100
THD-101
SNR-000
SNR-001
SNR-010
SNR-011
SNR-100
SNR-101
Figure 84. SNR and THD Performance vs. f
ADC
and ADC Bias Setting with
RxPGA = 0 dB, f
IN
= 10 MHz, and AIN = 1 dBFS
A sine wave input is a standard and convenient method of
analyzing the performance of a system. However, the amount of
power reduction that is possible is application dependent, based
on the nature of the input waveform (such as frequency content,
peak-to-rms ratio), the minimum ADC sample, and the mini-
mum acceptable level of performance. Thus, it is advisable that
power-sensitive applications optimize the power bias setting of
the Rx path using an input waveform that is representative of
the application.
POWER DISSIPATION
The power dissipation of the AD9865 can become quite high in
full-duplex applications in which the Tx and Rx paths are si-
multaneously operating with nominal power bias settings. In
fact, some applications that use the IAMP may need to either
reduce its peak power capabilities or reduce the power con-
sumption of the Rx path, so that the device’s maximum
allowable power consumption, P
MAX
, is not exceeded.
P
MAX
is specified at 1.66 W to ensure that the die temperature
does not exceed 125
o
C at an ambient temperature of 85
o
C. This
specification is based on the 64-pin LFSCP having a thermal
resistance, θ
JA
, of 24
o
C/W with its heat slug soldered. (The θ
JA
is
30.8
o
C/W, if the heat slug remains unsoldered.) If a particular
application’s maximum ambient temperature, T
A
, falls below
85
o
C, the maximum allowable power dissipation can be deter-
mined by the following equation:
P
MAX
= 1.66 + (85
T
A
)/24
(13)
Assuming the IAMP’s common-mode bias voltage is operating
off the same analog supply as the AD9865, the following equa-
tion can be used to calculate the maximum total current
consumption, I
MAX
, of the IC:
I
MAX
= (
P
MAX
P
IAMP
)/3.47
(14)
With an ambient temperature of up to 85°C, I
MAX
is 478 mA.
If the IAMP is operating off a different supply or in the voltage
mode configuration, first calculate the power dissipated in the
IAMP, P
IAMP
, using Equation 2 or Equation 5, and then
recalculate I
MAX
, using Equation 14.
Figure 78, Figure 79, Figure 81, and Figure 83 can be used to
calculate the current consumption of the Rx and Tx paths for a
given setting.
MODE SELECT UPON POWER-UP AND RESET
The AD9865 power-up state is determined by the logic levels
appearing at the MODE and CONFIG pins. The MODE pin is
used to select a half- or full-duplex interface by pin strapping it
low or high, respectively. The CONFIG pin is used in conjunc-
tion with the MODE pin to determine the default settings for
the SPI registers as outlined in Table 10.
The intent of these particular default settings is to allow some
applications to avoid using the SPI (disabled by pin-strapping
SEN high), thereby reducing implementation costs. For
example, setting MODE low and CONFIG high configures the
AD9865 to be backward compatible with the AD9975, while
setting MODE high and CONFIG low makes it backward
compatible with the AD9875. Other applications must use the
SPI to configure the device.
A hardware
(RESET pin) or software
(Bit 5 of Register 0x00)
reset can be used to place the AD9865 into a known state of
operation as determined by the state of the MODE and
CONFIG pins. A dc offset calibration and filter tuning routine
is also initiated upon a hardware reset, but not with a software
reset. Neither reset method flushes the digital interpolation
filters in the Tx path. Refer to the Half-Duplex Mode and Full-
Duplex Mode sections for information on flushing the digital
filters.
A hardware
reset can be triggered by pulsing the RESET pin low
for a minimum of 50 ns. The SPI registers are instantly reset to
their default settings upon RESET going low, while the dc offset
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