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參數(shù)資料
| 型號： | AD9857AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 551K |
| 代理商： | AD9857AST |
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AD9857
–13–
REV. 0
-
T
DH
T
DS
T
DS
T
DH
I
0
TxENABLE
PDCLK
D<13:0>
Q
N
I
N
Q
1
I
1
Q
0
Figure 19. 14-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode
T
DH
I
K
–
1
I
1
T
DS
T
DS
T
DH
I
0
TxENABLE
PDCLK
D<13:0>
I
2
I
3
I
K
T
DS
IS THE DATA SETUP TIME
T
DH
IS THE DATA HOLD TIME
Figure 20. 14-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
(see the Profile section) to be transferred to the accumulator of
the DDS, thus starting the frequency synthesis process.
After loading the frequency tuning word to a profile, a FUD signal
is not needed when switching between profiles using the two profile
select pins (PS0, PS1). When switching between profiles, the fre-
quency tuning word in the profile register is becomes effective.
In the Quadrature Modulation mode the PDCLK rate is
twice
the rate of the I (or Q) data rate. The AD9857 expects interleaved
I and Q data words at the parallel port with one word per PDCLK
rising edge. One I word and one Q word together comprise one
internal
sample
. Each sample is propagated along the internal
data pathway in parallel.
In the Interpolating DAC mode, however, the PDCLK rate is
the same as the “I” data rate since the “Q” data path is inactive.
In this mode, each PDCLK rising edge latches a data word into
the “I” data path.
The PDCLK is provided as a continuous clock (i.e., always
active). However, the assertion of PDCLK may be optionally
qualified internally by the PLL Lock Indicator if the user elects to
set the PLL Lock Control bit in the appropriate Control Register.
Data supplied by the user to the 14-bit Parallel Port is latched
into the device coincident with the rising edge of the PDCLK.
In the Quadrature Modulation Mode the rising edge of the
TxENABLE signal is used to synchronize the device. While
TxENABLE is in the Logic 0 state, the device ignores the 14-bit
data applied to the parallel port and allows the internal data path to
be flushed by forcing 0s down the I and Q data pathway. On the
rising edge of TxENABLE the device is ready for the first “I”
word. The first “I” word is latched into the device coincident with
the rising edge of PDCLK. The next rising edge of PDCLK
latches in a “Q” word, etc., until TxENABLE is set to a Logic 0
state by the user.
When in the Quadrature Modulation Mode it is important that
the user ensure that an even number of PDCLK intervals are
observed during any given TxENABLE period. This is because
the device must capture
both
an I and a Q value before the data
can be processed along the internal data pathway.
The timing relationship between TxENABLE, PDCLK, and
DATA is shown in Figures 19 and 20.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9857ASTZ | 功能描述:IC QUADRATURE DGTL UPCONV 80LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:AD9857 標(biāo)準(zhǔn)包裝:100 系列:* |
| AD9857ASTZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9857ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9857ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9858 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
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