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參數(shù)資料
| 型號： | AD9852AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300 MHz Complete-DDS |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 20 MHz, PQFP80 |
| 封裝： | MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 22/42頁 |
| 文件大?。?/td> | 424K |
| 代理商： | AD9852AST |
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AD9852
–22–
REV. 0
FM Chirp
Figure 46 graphically illustrates the effect of CLR ACC2 bit
upon the DDS output frequency. Note that reprogramming the
registers while the CLR ACC2 bit is high allows a new FTW1
frequency and slope to be loaded.
Another function available only in the chirp mode is the HOLD
pin, Pin 29. This function will stop the clocking signal to the ramp
rate counter that will, in turn, halt any further clocking pulses to
the frequency accumulator, ACC1. The effect is to halt the
chirp and hold the output frequency in a static condition at
the frequency existing just before HOLD was pulled high. When
the HOLD pin is returned low, the clocks are resumed and chirp
continues. During a hold condition, user may change the
programming registers; however, the ramp rate counter must
resume operation at its previous rate until a count of zero is
obtained before a new ramp rate count can be loaded. Figure 47
illustrates the effect of the hold function on the DDS output
frequency.
Users may utilize the 32-bit automatic I/O Update counter when
constructing complex chirp or ramped FSK sequences. Since
this internal counter is synchronized with the AD9852 System
UPDATE
CLOCK
F1
0
F
MODE
FTW1
DFW
F1
000 (DEFAULT)
0
RAMP RATE
RAMP RATE
011 (CHIRP)
DELTA FREQUENCY WORD
CLR ACC1
Figure 45. Effect of CLR ACC1 in FM Chirp Mode
CLR ACC2
F1
0
F
MODE
TW1
DPW
000 (DEFAULT)
0
RAMP RATE
011 (CHIRP)
Figure 46. Effect of CLR ACC2 in FM Chirp Mode
Clock, it allows precisely timed program changes to be invoked.
In this manner, user is only required to reprogram the desired
registers before the automatic I/O Update pulse is generated.
A complete discussion of this function is presented elsewhere in
this data sheet.
In the chirp mode, the destination frequency is not directly
specified. If the user fails to control the chirp, the DDS will control
itself by naturally confining its output between dc and Nyquist;
however, unless terminated by the user, the chirp will continue
until power is removed.
It is the user’s choice as to what occurs when the chirp destination
frequency is reached. Here are a few of the choices:
1. Stop and hold at the destination frequency using the HOLD
pin, or by loading all zeros into the Delta Frequency Word
registers of the frequency accumulator (ACC1).
2. Stop using the hold pin function, then ramp-down the out-
put amplitude using the digital multiplier stages and the
Shaped Keying pin, Pin 30, or via program register control
(addresses 21–24 hex).
3. Stop and abruptly terminate the transmission using the CLR
ACC2 bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9852ASTZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASTZ | 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80 |
| AD9852ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852ASVZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASVZ | 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80 |
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