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參數(shù)資料
| 型號(hào)： | AD9852AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300 MHz Complete-DDS |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 20 MHz, PQFP80 |
| 封裝： | MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大?。?/td> | 424K |
| 代理商： | AD9852AST |
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AD9852
–15–
REV. 0
Finally, changing the logic state of Pin 30, “shaped keying” will
automatically perform the programmed output envelope functions
when OSK INT is high. A logic high on Pin 30 causes the out-
puts to linearly ramp up to full-scale amplitude and hold until
the logic level is changed to low, causing the outputs to ramp
down to zero-scale.
Cosine DAC
The cosine DAC generates the 300 MSPS (maximum) cosine
output of the DDS. The maximum output amplitude is set
by the DAC R
SET
resistor at Pin 56. This is a current-out DAC
with a full-scale maximum output of 20 mA; however, a nomi-
nal 10 mA output current provides best spurious-free dynamic
range (SFDR) performance. The value of R
SET
= 39.93/I
OUT
,
where I
OUT
is in amps. DAC output compliance specification lim-
its the maximum voltage developed at the outputs to –0.5 V to
+1 V. Voltages developed beyond this limitation will cause exces-
sive DAC distortion and possibly permanent damage. The user
must choose a proper load impedance to limit the output voltage
swing to the compliance limits. For best SFDR, both DAC outputs
should be terminated equally, especially at higher output fre-
quencies where harmonic distortion errors are more prominent.
The cosine DAC is preceded by inverse SIN(x)/x filters (a.k.a.
inverse sinc filter) that precompensate for DAC output amplitude
variations over frequency to achieve flat amplitude response from
dc to Nyquist. A digital multiplier follows the inverse sinc filters
to allow amplitude control, amplitude modulation and ampli-
tude shaped keying. The inverse sinc filter (address 20 hex, Bypass
Inv Sinc
bit)) and digital multiplier (address 20 hex, OSK EN
bit) can be bypassed for power conservation by setting those bits
high. Both DACs can be powered down by setting the DAC
PD
bit high (address 1D of control register) when not needed.
Cosine DAC outputs are designated as IOUT1 and IOUT1B,
Pins 48 and 49 respectively.
Control DAC
The 12-bit auxiliary, or control DAC can provide dc control
levels to external circuitry, generate ac signals, or duty cycle con-
trol, of the on-board comparator. The input twos complement
data is channeled through the serial or parallel interface to the
12-bit register (address 26 and 27 hex) at a maximum 100 MHz
data rate. This DAC is clocked at the system clock, 300 MSPS
(maximum), and has the same maximum output current capa-
bility as that of the cosine DAC. The single R
SET
resistor on the
AD9852 sets the full-scale output current for both cosine DAC
and the control DACs. The control DAC can be separately
powered down for power conservation when not needed by
setting the
Control DAC POWER-DOWN bit high (address
1D hex). Control DAC outputs are designated as IOUT2 and
IOUT2B (Pins 52 and 51 respectively).
0
CENTER 50MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10MHz/
SPAN 100MHz
IMAGES
FUNDAMENTAL OUTPUT POWER DECREASES
WITH INCREASING FREQUENCY
Figure 33. Normal SIN(x)/x DAC Output Power Envelope
Filter
0
CENTER 50MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10MHz/
SPAN 100MHz
FUNDAMENTAL OUTPUT POWER IS
"FLAT" FROM DC TO 1/2 FCLK
Figure 34. Inverse SIN(x)/x (Inverse Sinc) Filter Engaged
Inverse SINC Function
This filter precompensates input data to the cosine DAC for
the SIN(x)/x roll-off function to allow wide bandwidth signals
(such as QPSK) to be output from the DACs without appreciable
amplitude variations that will cause increased EVM (error vector
magnitude). The inverse SINC function may be bypassed to
significantly
reduce power consumption, especially at higher
clock speeds. Inverse sinc is engaged by default and is bypassed
by bringing the “Bypass Inv Sinc” bit high in control register 20
(hex) in Table V.
REFCLK Multiplier
This is a programmable PLL-based reference clock multiplier
that allows the user to select an integer clock multiplying value
over the range of 4
×
to 20
×
by which the REFCLK input will be
multiplied. Use of this function allows users to input as little as
15 MHz to produce a 300 MHz internal system clock
.
Five bits
in control register 1E hex set the multiplier value as follows in
Table I.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9852ASTZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASTZ | 制造商:Analog Devices 功能描述:IC DDS 100MHZ LQFP-80 |
| AD9852ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Complete DDS |
| AD9852ASVZ | 功能描述:IC DDS SYNTHESIZER CMOS 80-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9852ASVZ | 制造商:Analog Devices 功能描述:IC DDS 300MHz TQFP-80 制造商:Analog Devices 功能描述:IC, DDS, 300MHz, TQFP-80 |
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