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參數(shù)資料
| 型號： | AD9850 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS,125 MHz Complete DDS Synthesizer |
| 中文描述： | CMOS，125 MHz的完整的DDS合成器 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 304K |
| 代理商： | AD9850 |
AD9850
–9–
REV. B
CLK
OUT
PHASE
ACCUMULATOR
TUNING WORD SPECIFIES
OUTPUT FREQUENCY
AS A FRACTION OF REF
CLOCK FREQUENCY
N
AMPLITUDE/COS
CONV.
ALGORITHM
DDS CIRCUITRY
D/A
CONVERTER
LP
COMPARATOR
REF
CLOCK
IN DIGITAL DOMAIN
COS (x)
Figure 16. Basic DDS Block Diagram and Signal Flow of AD9850
The reference clock frequency of the AD9850 has a minimum
limitation of 1 MHz. The device has internal circuitry that
senses when the minimum clock rate threshold has been exceeded
and automatically places itself in the power-down mode. When
in this state, if the clock frequency again exceeds the threshold,
the device resumes normal operation. This shutdown mode
prevents excessive current leakage in the dynamic registers of
the device.
The D/A converter output and comparator inputs are available
as differential signals that can be flexibly configured in any
manner desired to achieve the objectives of the end-system. The
typical application of the AD9850 is with single-ended output/
input analog signals, a single low-pass filter, and generating the
comparator reference midpoint from the differential DAC out-
put as shown in Figure 13.
Programming the AD9850
The AD9850 contains a 40-bit register that is used to program the
32-bit frequency control word, the 5-bit phase modulation word
and the power-down function. This register can be loaded in a
parallel or serial mode.
In the parallel load mode, the register is loaded via an 8-bit bus;
the full 40-bit word requires five iterations of the 8-bit word.
The W_CLK and FQ_UD signals are used to address and load
the registers. The rising edge of FQ_UD loads the (up to) 40-bit
control data word into the device and resets the address pointer
to the first register. Subsequent W_CLK rising edges load the
8-bit data on words [7:0] and move the pointer to the next
register. After
five
loads, W_CLK edges are ignored until either
a reset or an FQ_UD rising edge resets the address pointer to
the first register.
In serial load mode, subsequent rising edges of W_CLK shift
the 1-bit data on Lead 25 (D7) through the 40 bits of program-
ming information. After 40 bits are shifted through, an FQ_UD
pulse is required to update the output frequency (or phase).
The function assignments of the data and control words are
shown in Table III; the detailed timing sequence for updating
the output frequency and/or phase, resetting the device, and
powering-up/down, are shown in the timing diagrams of Figures
18–24.
Note: There are specific control codes, used for factory test
purposes, that render the AD9850 temporarily inoperable. The
user must take deliberate precaution to avoid inputting the
codes listed in Table II.
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy as manifested in the low
jitter performance of the AD9850. Since the output of the
AD9850 is a sampled signal, its output spectrum follows the
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the Reference Clock Frequency
±
the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 17.
20MHz
FUNDAMENTAL
80MHz
1ST IMAGE
120MHz
2ND IMAGE
100MHz
REFERENCE CLOCK
FREQUENCY
180MHz
3RD IMAGE
220MHz
4TH IMAGE
280MHz
5TH IMAGE
fc
fc+fo
fc–fo
2fc–fo
2fc+fo
3fc–fo
f
OUT
sin(x)/x ENVELOPE x=(pi)fo/fc
S
Figure 17. Output Spectrum of a Sampled Signal
In this example, the reference clock is 100 MHz and the output
frequency is set to 20 MHz. As can be seen, the aliased images
are very prominent and of a relatively high energy level as deter-
mined by the sin(x)/x roll-off of the quantized D/A converter
output. In fact, depending on the fo/Ref Clk relationship, the
first aliased image can be on the order of –3 dB below the fun-
damental. A low-pass filter is generally placed between the out-
put of the D/A converter and the input of the comparator to
further suppress the effects of aliased images. Obviously, con-
sideration must be given to the relationship of the selected
output frequency and the Reference Clock frequency to avoid
unwanted (and unexpected) output anomalies.
A good rule-of-thumb for applying the AD9850 as a clock
generator is to limit the selected output frequency to <33% of
Reference Clock frequency, thereby avoiding generating aliased
signals that fall within, or close to, the output band of interest
(generally dc-selected output frequency). This practice will ease
the complexity (and cost) of the external filter requirement for
the clock generator application.
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| AD9850BRS-REEL | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9850BRSZ | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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