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參數(shù)資料
| 型號： | AD9850 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS,125 MHz Complete DDS Synthesizer |
| 中文描述： | CMOS，125 MHz的完整的DDS合成器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 304K |
| 代理商： | AD9850 |
AD9850BRS
Min
Typ
Parameter
Temp
Test Level
Max
Units
CMOS LOGIC INPUTS (Including CLKIN)
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
I
I
I
I
I
V
3.5
3.0
V
V
V
μ
A
μ
A
pF
0.4
12
12
3
POWER SUPPLY (A
OUT
= 1/3 CLKIN)
+V
S
Current @:
62.5 MHz Clock, +3.3 V Supply
110 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
P
DISS
@:
62.5 MHz Clock, +3.3 V Supply
110 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
P
DISS
Power-Down Mode
+5 V Supply
+3.3 V Supply
FULL
FULL
FULL
FULL
VI
VI
VI
VI
30
47
44
76
48
60
64
96
mA
mA
mA
mA
FULL
FULL
FULL
FULL
VI
VI
VI
VI
100
155
220
380
160
200
320
480
mW
mW
mW
mW
FULL
FULL
V
V
30
10
mW
mW
NOTES
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*
AD9850BRS
Min
Parameter
Temp
Test Level
Typ
Max
Units
t
DS
(Data Setup Time)
t
DH
(Data Hold Time)
t
WH
(W_CLK min. Pulsewidth High)
t
WL
(W_CLK min. Pulsewidth Low)
t
WD
(W_CLK Delay After FQ_UD)
t
CD
(CLKIN Delay After FQ_UD)
t
FH
(FQ_UD High)
t
FL
(FQ_UD Low)
t
CF
(Output Latency from FQ_UD)
Frequency Change
Phase Change
t
FD
(FQ_UD Min. Delay After W_CLK)
t
RH
(CLKIN Delay After RESET Rising Edge)
t
RL
(RESET Falling Edge After CLKIN)
t
RS
(Minimum RESET Width)
t
OL
(RESET Output Latency)
t
RR
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
IV
IV
IV
IV
IV
IV
IV
IV
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
+25
°
C
IV
IV
IV
IV
IV
IV
IV
IV
V
18
13
7.0
3.5
3.5
5
13
2
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
μ
s
5
NOTES
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
(V
S
= +5 V
6
5% except as noted, R
SET
= 3.9 k
V
)
REV. B
–3–
AD9850
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| AD9850/CGPCB | 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850/FSPCB | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER 制造商:Analog Devices 功能描述:NCO/DDS, CMOS, 125MHZ COMPLETE DDS SYNTHESIZER - Bulk |
| AD9850BRS | 功能描述:IC DDS DAC W/COMP 125MHZ 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9850BRS-REEL | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9850BRSZ | 功能描述:IC DDS SYNTHESIZER CMOS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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