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參數(shù)資料
| 型號(hào)： | AD9846AJSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 10BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
REV. 0
AD9846A
–17–
CIRCUIT DESCRIPTION AND OPERATION
The AD9846A signal processing chain is shown in Figure 25.
Each processing step is essential in achieving a high-quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc-
restore circuit is used with an external 0.1
F series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V single supply of
the AD9846A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on
the rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (tID) of 3 ns is caused by internal
propagation delays.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. Unlike some AFE architectures, the AD9846A
removes this offset in the input stage to minimize the effect of a
gain change on the system black level, usually called the “gain
step.” Another advantage of removing this offset at the input
stage is to maximize system headroom. Some area CCDs have
large black level offset voltages, which, if not corrected at the
input stage, can signicantly reduce the available headroom in
the internal circuitry when higher VGA gain settings are used.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
together with CLPOB or separately. The CLPDM pulse should
be a minimum of 4 pixels wide.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplier with four separate
values, the PxGA has the capability to “multiplex” its gain value
on a pixel-to-pixel basis. This allows lower output color pixels to
be gained up to match higher output color pixels. Also, the PxGA
may be used to adjust the colors for white balance, reducing the
amount of digital processing that is needed. The four different gain
values are switched according to the “Color Steering” circuitry.
Seven different color steering modes for different types of CCD
color lter arrays are programmed in the AD9846A’s Control
Register. For example, Mosaic Separate steering mode accom-
modates the popular “Bayer” arrangement of Red, Green, and
Blue lters (see Figure 26).
2dB TO 36dB
CLPDM
CCDIN
DIGITAL
FILTERING
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
0.1 F
DOUT
10-BIT
ADC
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
10
CDS
INPUT OFFSET
CLAMP
INTERNAL
VREF
2V FULL SCALE
COLOR
STEERING
4:1
MUX
3
GAIN0
GAIN1
GAIN2
GAIN3
PxGA
–2dB TO +10dB
PxGA MODE
SELECTION
2
6
VD
HD
PxGA GAIN
REGISTERS
10
Figure 25. CCD-Mode Block Diagram
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| AD9846AJSTZRL | 功能描述:IC CCD SIGNAL PROC 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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| AD9847 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver |
| AD9847AKCPZ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9847AKCPZRL | 制造商:Analog Devices 功能描述:DISPLAY DRVR, 10-BIT 40MSPS CCD SGNL PROCESSOR W/ INTEGRATED - Tape and Reel |
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