參數(shù)資料
型號(hào)： AD9846AJSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/24頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC 10BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，10 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
REV. 0
AD9846A
–19–
AUX1IN
0.1 F
VGA GAIN
REGISTER
ADC
VGA
10
5k
0.4V
INPUT SIGNAL
??V
0.8V
0.4V
MIDSCALE
0dB TO 36dB
Figure 30. AUX1 Circuit Conguration
0dB TO 18dB
8
AUX2IN
BUFFER
0.1 F
VIDEO
SIGNAL
9
CLAMP LEVEL
LPF
VGA GAIN
REGISTER
ADC
VGA
VIDEO CLAMP
CIRCUIT
CLAMP LEVEL
REGISTER
Figure 31. AUX2 Circuit Conguration
Table VII. VGA Gain Register Used for AUX2-Mode
MSB
LSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (dB)
X0
XXXXXXXXX0.0
10000000000.0
111111111118.0
A/D Converter
The AD9846A uses high-performance ADC architecture, opti-
mized for high speed and low power. Differential Nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9846A ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range (see TPC 3).
AUX1 Mode
For applications that do not require CDS, the AD9846A can be
configured to sample ac-coupled waveforms. Figure 30 shows
the circuit configuration for using the AUX1 channel input
(Pin 36). A single 0.1
F ac-coupling capacitor is needed between
the input signal driver and the AUX1IN pin. An on-chip dc-bias
circuit sets the average value of the input signal to approximately
0.4 V, which is referenced to the midscale code of the ADC.
The VGA Gain register provides a gain range of 0 dB to 36 dB in
this mode of operation (see VGA Gain Curve, Figure 29).
The VGA gains up the signal level with respect to the 0.4 V bias
level. Signal levels above the bias level will be further increased
to a higher ADC code, while signal levels below the bias level
will be further decreased to a lower ADC code.
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). A
external 0.1
F blocking capacitor is used with the on-chip video
clamp circuit, to level-shift the input signal to a desired refer-
ence level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the Clamp
Level register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VII.)
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