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| 型號： | AD9803JST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor For Electronic Cameras |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 179K |
| 代理商： | AD9803JST |
AD9803
–11–
REV. 0
THEORY OF OPERATION
Introduction
The AD9803 is a 10-bit analog-to-digital interface for CCD
cameras. The block level diagram of the system is shown in
Figure 23. The device includes a correlated double sampler
(CDS), 0 dB–30 dB programmable gain amplifier (PGA), black
level correction loop, input clamp and voltage reference. The
only external analog circuitry required at the system level is an
emitter follower buffer between the CCD output and AD9803
inputs.
CLPDM
INPUT CLAMP
PIN
DIN
CDS
SHA
ADC
INTEG
BLACK LEVEL CLAMP
PGA
DIFFERENTIAL SIGNAL PATH
CLPOB
Figure 23. CCD Mode Signal Path
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a
method for removing several types of noise. Basically, two
samples of the CCD output are taken: one with the signal
present (“data”) and one without (“reference”). Subtracting
these two samples removes any noise which is common—or
correlated—to both.
Figure 24 shows the block diagram of the AD9803’s CDS. The
S/H blocks are directly driven by the input and the sampling
function is performed passively, without the use of amplifiers.
This implementation relies on the off-chip emitter follower
buffer to drive the two 10 pF sampling capacitors. Only one
capacitor at a time is seen at the input pin.
10pF
Q1
S/H
Q2
S/H
S
OUT
FROM
CCD
Figure 24. CDS Block Diagram
The AD9803 actually uses two CDS circuits in a “ping pong”
fashion to allow the system more acquisition time. In this way,
the output from one of the two CDS blocks will be valid for an
entire clock cycle. Thus, the bandwidth requirement of the
subsequent gain stage is reduced as compared to that for a single-
channel CDS system. This lower bandwidth translates to lower
power and noise.
Programmable Gain Amplifier (PGA)
The on-chip PGA provides a gain range of 0 dB–30 dB, which
is “l(fā)inear in dB.” Typical gain characteristics are shown in
Figures 25 and 26.
40
G
PGACONT1 – Volts
0
35
30
25
20
15
10
5
0
–5
0.5
1.0
1.5
2.0
2.5
3.0
Figure 25. PGA Gain Curve—Analog Control
40
G
PGA GAIN REGISTER
0
35
30
25
20
15
10
5
0
–5
1023
171
341
511
682
852
Figure 26. PGA Gain Curve—Digital Control
As shown in Figure 27, analog PGA control is provided through
the PGACONT1 and PGACONT2 inputs. PGACONT1 pro-
vides coarse and PGACONT2 fine (1/16) gain control. The
PGA gain can also be controlled using the internal 10-bit DAC
through the serial digital interface. The gain characteristic
shown in Figure 26, with the internal DAC providing the same
control range as PGACONT1. See the Serial Interface Specifi-
cations for more details.
A
PGACONT1
PGACONT2
PGACONT1 = COARSE CONTROL
PGACONT2 = FINE (1/16) CONTROL
Figure 27. Analog PGA Control
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9803JST-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9803JSTRL-28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9804 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9804AJST | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MHZ NO PXGA - Tape and Reel |
| ad9804ajstrl | 制造商:Analog Devices 功能描述:CCD Signal Processor 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MHZ NO PXGA - Tape and Reel |
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