參數(shù)資料
型號: AD9786-EBZ
廠商: Analog Devices Inc
文件頁數(shù): 32/56頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9786
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC+®
DAC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 500M
數(shù)據(jù)接口: 并聯(lián)
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: AD9786
AD9786
Rev. B | Page 38 of 56
POWER DISSIPATION
The AD9786 has seven power-supply domains: two 3.3 V
analog domains (AVDD1 and AVDD2), two 2.5 V analog
domains (ADVDD and ACVDD), one 2.5 V clock domain
(CLKVDD), and two digital domains (DVDD, which runs
from 2.5 V; and DRVDD, which runs from 3.3 V).
The current needed for the 3.3 V analog supplies, AVDD1 and
AVDD2, is consistent across speed and varying modes of the
AD9786. Nominally, the current for AVDD1 is 29 mA across all
speeds and modes, whereas the current for AVDD2 is 20 mA.
The current for the 2.5 V analog supplies and the digital
supplies varies depending on speed and mode of operation.
Figure 67, Figure 68, and Figure 69 show this variation. Note
that CLKVDD, ADVDD, and ACVDD vary with clock speed
and interpolation rate, but not with modulation rate.
03152-067
FDATA (MSPS)
250
0
25
50
75
100
125
150
175
200
225
IDV
DD
(mA)
0
425
325
300
275
250
225
200
175
400
375
350
150
125
100
75
50
25
2× fs/4
2× fs/8
4× fs/4
4× fs/8
8× fs/4
8× fs/8
Figure 67. DVDD Supply Current vs. Clock Speed,
Interpolation, and Modulation Rates
03152-068
FDATA (MSPS)
250
0
25
50
75
100
125
150
175
200
225
ICLKV
DD
(mA)
0
60
50
40
30
20
10
Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates
03152-069
FDATA (MSPS)
250
0
25
50
75
100
125
150
175
200
225
IADV
DD
AND
IACV
DD
(mA)
0
30
25
20
15
10
5
Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed
and Interpolation Rates
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