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參數(shù)資料
| 型號： | AD977A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 200 kSPS BiCMOS A/D Converter(200kSPS 16位A/D轉(zhuǎn)換器) |
| 中文描述： | 16位，200 kSPS的BiCMOS工藝的A / D轉(zhuǎn)換器（速度高達(dá)200ksps的16位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 287K |
| 代理商： | AD977A |
AD977/AD977A
–21–
REV. A
USE OF THE TAG INPUT
The AD977/AD977A provides a TAG input pin for cascading
multiple converters together. This feature is useful for reducing
component count in systems where an isolation barrier must be
crossed and is also useful for systems with a limited capacity for
interfacing to a large number of converters.
The tag feature only works in the external clock mode and re-
quires that the DATA output of a “upstream” device be con-
nected to the TAG input of an “downstream” device.
An example of the concatenation of two devices is shown in
Figure 25 and their resultant output is shown in Figure 26.
In Figure 25, the paralleled R/
C
ensures that each AD977/
AD977A will simultaneously sample their inputs. In Figure 26,
a “null” bit is shown between each 16-bit word associated with
each ADC in the serial data output stream. This is the result of
a minimum value for “External Data Clock to Data Valid Delay”
(t
18
) that is greater than the “TAG Valid Setup Time” (t
23
). In
other words, when you concatenate two or more AD977/AD977As
the MSB on the downstream device will not be present on the
TAG input of the upstream device in time to meet the setup
time requirement of the TAG input.
If the serial data stream is going to a parallel port of a micro-
processor that is also providing the serial data clock, then the
microprocessor’s firmware can be written to “throw away” the
null bit. If the serial data stream is going to a serial port then
external “glue” logic will have to be added to make the interface
work. If the serial port has a “sync” input then this can be used
to throw away the null bit if the sync input is toggled each time
the null bit appears.
If the application does not require simultaneous sampling, the
null bit can be completely avoided by delaying the R/
C
signal
of each upstream device by one clock cycle with respect to its
immediate downstream device. This bit time delay can be ac-
complished through a D-type flip-flop that delays the R/
C
signal
at its D-input by one cycle of the serial data clock that is at its
clock input.
DATA OUT
DCLK IN
R/ IN
IN
TAG
DATA
DCLK
AD977/AD977A
#2
(UPSTREAM)
AD977/AD977A
#1
(DOWNSTREAM)
TAG
DATA
DCLK
CS
R/C
CS
R/C
Figure 25. Two AD977/AD977A’s Utilizing Tag
It is not recommended that the TAG feature be used with the
read during convert mode because this will require data to be
clocked out during the second half of the conversion process. It
is recommended that the read after convert mode be used in an
application that wants to take advantage of the TAG feature. To
improve the data throughput a combination of the two data read
methods can be used and is described as follows.
If two or more AD977/AD977As are to have their data output
concatenated together in a single data stream, and if data
throughput is to be maximized, a system could be designed such
that the upstream device data is read during the first half of its
conversion process and the remainder of the downstream de-
vices read during the time between conversions. Assume three
AD977As are to have their data concatenated. Assume the
further most downstream device is referred to as device #1 and
the further most upstream device as #3. Each device is driven
from a common DATACLK and R/
C
control signal, the
CS
input of each device is tied to ground. The three
BUSY
outputs
should be OR’d together to form a composite
BUSY
. After the
conversion is complete, as indicated by the composite
BUSY
going high, an external, normally low, 15.15 MHz DATACLK
can be toggled 34 times to first read the data first from device
#3 and then from device #2. When the composite BUSY goes
low to indicate the beginning of the conversion process the
external DATACLK can be toggled 17 times to read the data
from device #1 during the first half of the conversion process.
Using this technique it would be possible to read in the data
from the three devices in approximately 6.4
μ
s for a throughput
of approximately 156 kHz The receiving device would have to
deal with the null bit between data from device #2 and #3. The
receiving device would also have to be capable of starting and
stopping the external DATACLK at the appropriate times.
The TAG input, when unused, should always be tied either high
or low and not be allowed to float.
DATA
NULL BIT
DEVICE DATA #1
DEVICE
DATA #2
15
0
15
DCLK
R/
C
BUSY
Figure 26. TAG Timing Diagram for Two Concatenated
AD977/AD977As
POWER-DOWN FEATURE
The AD977/AD977A has analog and reference power-down
capability through the PWRD pin. When the PWRD pin is
taken high, the power consumption drops from a maximum
value of 100 mW to a typical value of 50
μ
W. When in the
power-down mode the previous conversion results are still avail-
able in the internal registers and can be read out providing it has
not already been shifted out.
When used with an external reference, connected to the REF
pin and a 2.2
μ
F capacitor, connected to the CAP pin, the
power up recovery time is typically 1 ms. This typical value of
1 ms for recovery time depends on how much charge has de-
cayed from the external 2.2
μ
F capacitor on the CAP pin and
assumes that it has decayed to zero. The 1 ms recovery time has
been specified such that settling to 16-bits has been achieved.
When used with the internal reference, the dominant time con-
stant for power-up recovery is determined by the external ca-
pacitor on the REF pin and the internal 4K impedance seen at
that pin. An external 2.2
μ
F capacitor is recommended for the
REF pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD977AAN | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 16-bit Serial 20-Pin PDIP N 制造商:Analog Devices 功能描述:IC 16BIT ADC DIP20 977 |
| AD977AANZ | 功能描述:IC ADC 16BIT 200KSPS 20DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD977AAR | 功能描述:IC ADC 16BIT 200KSPS 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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| AD977AARSZ | 功能描述:IC ADC 16BIT 200KSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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