- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD977 (Analog Devices, Inc.) 16-Bit, 100 kSPS BiCMOS A/D Converter(100kSPS 16位A/D轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號： | AD977 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 100 kSPS BiCMOS A/D Converter(100kSPS 16位A/D轉(zhuǎn)換器) |
| 中文描述： | 16位，100 kSPS的BiCMOS工藝的A / D轉(zhuǎn)換器（100ksps的16位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 287K |
| 代理商： | AD977 |
AD977/AD977A
–6–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin No.
DIP/SOIC
Pin No.
SSOP
MNEMONIC
DESCRIPTION
1, 3, 4
2
5
1, 3, 4
2
6
R1
IN
, R2
IN
, R3
IN
AGND1
CAP
Analog Input. Refer to Table I, Table II for input range configuration.
Analog Ground. Used as the ground reference point for the REF pin.
Reference buffer output. Connect a 2.2
μ
F tantalum capacitor between CAP and
Analog Ground.
Reference Input/Output. The internal +2.5 V reference is available at this pin.
Alternatively an external reference can be used to override the internal reference.
In either case, connect a 2.2
μ
F tantalum capacitor between REF and Analog Ground.
Analog Ground.
This digital input is used to select the data format of a conversion result. With SB/
BTC
tied LOW, conversion data will be output in Binary Twos Complement format. With
SB/
BTC
connected to a logic HIGH, data is output in Straight Binary format.
Digital select input for choosing the internal or an external data clock. With EXT/
INT
tied LOW, after initiating a conversion, 16 DATACLK pulses transmit the previous
conversion result as shown in Figure 3. With EXT/
INT
set to a logic HIGH, output
data is synchronized to an external clock signal connected to the DATACLK input.
Data is output as indicated in Figure 4 through Figure 9.
Digital Ground.
Digital output frame synchronization for use with an external data clock
(EXT/
INT
= Logic HIGH). When a read sequence is initiated, a pulse one
DATACLK period wide is output synchronous to the external data clock.
Serial data clock input or output, dependent upon the logic state of the EXT/
INT
pin. When using the internal data clock (EXT/
INT
= Logic LOW), a conversion
start sequence will initiate transmission of 16 DATACLK periods. Output data is
synchronous to this clock and is valid on both its rising and falling edges (Figure 3).
When using an external data clock (EXT/
INT
= Logic HIGH), the
CS
and R/
C
signals control how conversion data is accessed.
The serial data output is synchronized to DATACLK. Conversion results are
stored in an on-chip register. The AD977 provides the conversion result, MSB
first, from its internal shift register. The DATA format is determined by the logic
level of SB/
BTC
. When using the internal data clock (EXT/
INT
= Logic LOW),
DATA is valid on both the rising and falling edges of DATACLK. Between conver-
sions DATA will remain at the level of the TAG input when the conversion was
started. Using an external data clock (EXT/
INT
= Logic HIGH) allows previous
conversion data to be accessed during a conversion (Figures 5, 7 and 9) or the
conversion result can be accessed after the completion of a conversion (Figures 4, 6
and 8).
This digital input can be used with an external data clock, (EXT/
INT
= Logic
HIGH) to daisy chain the conversion results from two or more AD977s onto a
single DATA line. The digital data level on TAG is output on DATA with a delay
of 16 or 17 external DATACLK periods after the initiation of the read sequence.
Dependent on whether a SYNC is not present or present.
Read/Convert Input. Is used to control the conversion and read modes of the
AD977. With
CS
LOW; a falling edge on R/
C
holds the analog input signal inter-
nally and starts a conversion, a rising edge enables the transmission of the conver-
sion result.
Chip Select Input. With R/
C
LOW, a falling edge on
CS
will initiate a conversion.
With R/
C
HIGH, a falling edge on
CS
will enable the serial data output sequence.
Busy Output. Goes LOW when a conversion is started, and remains LOW until the
conversion is completed and the data is latched into the on-chip shift register.
Power-Down Input. When set to a logic HIGH power consumption is reduced and
conversions are inhibited. The conversion result from the previous conversion is
stored in the onboard shift register.
Analog Power Supply. Nominally +5 V.
Digital Power Supply. Nominally +5 V.
6
7
REF
7
8
9
12
AGND2
SB/
BTC
9
13
EXT/
INT
10
11
14
15
DGND
SYNC
12
16
DATACLK
13
17
DATA
14
19
TAG
15
21
R/
C
16
24
CS
17
25
BUSY
18
26
PWRD
19
20
27
28
V
ANA
V
DIG
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD977A | 16-Bit, 200 kSPS BiCMOS A/D Converter(200kSPS 16位A/D轉(zhuǎn)換器) |
| AD9803JST | CCD Signal Processor For Electronic Cameras |
| AD9804 | Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9804JST | Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9850BRS | CMOS, 125 MHz Complete DDS Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 150 MSPS TxDAC⑩ with 2x Interpolation Filter |
| AD9772A | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| AD9772AAST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14BIT 160 MSPS TXDAC+ W/2X INTERPOLATION - Tape and Reel 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Number of Bi |
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
發(fā)布緊急采購，3分鐘左右您將得到回復。