參數(shù)資料
型號(hào)： AD9779ABSVZRL
廠商： Analog Devices Inc
文件頁數(shù)： 37/56頁
文件大?。?/td> 0K
描述： DAC 16BIT 1.0GSPS 100-TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 300mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 1G
AD9776A/AD9778A/AD9779A
Rev. B | Page 42 of 56
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
The signal level can range from 400 mV p-p differential to
1.6 V p-p differential centered about a 400 mV input common-
mode voltage. Looking at the single-ended inputs, REFCLK+ or
REFCLK, each input pin can safely swing from 200 mV p-p to
800 mV p-p about the 400 mV common-mode voltage. Although
these input levels are not directly LVDS compatible, REFCLK
can be driven by an offset ac-coupled LVDS signal, as shown in
LVDS_P_IN
REFCLK+
50
0.1F
LVDS_N_IN
REFCLK–
VCM = 400mV
0
645
2-
0
68
Figure 73. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 73. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, and then ac-coupled as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 74.
50
TTL OR CMOS
CLK INPUT
REFCLK+
REFCLK–
VCM = 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1F
06
452
-06
9
Figure 74. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating VCM is shown in Figure 75.
It is important to use CVDD18 and CGND for the clock bias
circuit. Any noise or other signal that is coupled onto the clock
is multiplied by the DAC digital input signal and can degrade
DAC performance.
0.1F
1nF
VCM = 400mV
CVDD18
CGND
1k
287
06
45
2-
0
70
Figure 75. REFCLK VCM Generator Circuit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9779A-DPG2-EBZ 功能描述:BOARD EVALUATION FOR AD9779A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9779A-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk
AD9779AMOD-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk
AD9779AXSVZ 制造商:Analog Devices 功能描述:DUAL 16-BIT, 1 GSPS, DIGITAL-TO-ANALOG CONVERTER - Bulk
AD9779BSV 制造商:Analog Devices 功能描述:DAC 2CH INTERPOLATION FLTR 16BIT 100TQFP EP - Bulk
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