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參數(shù)資料
| 型號： | AD9776BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL 1GSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9776/AD9778/AD9779
Rev. A | Page 36 of 56
LVDS_P_IN
CLK+
50
Ω
50
Ω
0.1
μF
0.1
μF
LVDS_N_IN
CLK–
VCM = 400mV
05361-068
Figure 71. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 71. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 72.
50
Ω
50
Ω
TTL OR CMOS
CLK INPUT
CLK+
CLK–
VCM = 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1
μF
05361-069
Figure 72. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 73. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade DAC performance.
0.1
μF
1nF
VCM = 400mV
CVDD18
CGND
1k
Ω
287
Ω
05361-070
Figure 73. REFCLK VCM Generator Circuit
INTERNAL PLL CLOCK MULTIPLIER/CLOCK
DISTRIBUTION
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an
integer multiple of the input data rate or at the DAC output
sample rate. An internal PLL provides input clock multiplication
and provides all the internal clocks required for the interpolation
filters and data synchronization.
The internal clock architecture is shown in Figure 74. The
reference clock is the differential clock at Pin 5 and Pin 6. This
clock input can be run differentially or singled-ended by
driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
PLL Enabled (Register 0x09, Bit 7 = 1)
The PLL enable switch shown in Figure 74 is connected to the
junction of the N1 dividers (PLL VCO divide ratio) and N2
dividers (PLL loop divide ratio). Divider N3 determines the
interpolation rate of the DAC, and the ratio N3/N2 determines
the ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N1
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components are
entirely internal and no external compensation is necessary.
PLL Disabled (Register 0x09, Bit 7 = 0)
The PLL enable switch shown in Figure 74 is connected to the
reference clock input. The differential reference clock input is
the same as the DAC output sample rate. N3 determines the
interpolation rate.
ADC
PHASE
DETECTION
VCO
DAC
INTERPOLATION
RATE
INTERNAL
LOOP
FILTER
0x0A (4:0)
LOOP FILTER
BANDWIDTH
REFERENCE CLOCK
(PINS 5 AND 6)
0x0A (7:5)
PLL CONTROL
VOLTAGE RANGE
0x08 (7:2)
VCO RANGE
0x09 (7)
PLL ENABLE
INTERNAL DAC SAMPLE
RATE CLOCK
DATACLK OUT (PIN 37)
0x01 (7:6)
0x09 (6:5)
PLL VCO
DIVIDE RATIO
0x09 (4:3)
PLL LOOP
DIVIDE RATIO
÷N3
÷N2
÷N1
05361-
071
Figure 74. Internal Clock Architecture
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