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參數(shù)資料
| 型號： | AD9773EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | 12位，160 MSPS的2】/ 4】/ 8】TxDAC系列插雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 218K |
| 代理商： | AD9773EB |
AD9773
13
PRELIMINARY TECHNICAL DATA
B
S
M
B
S
L
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
I
W
/
R
1
N
0
N
4
A
3
A
2
A
1
A
0
A
N1
0
0
1
1
N0
0
1
0
1
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
Serial Interface For Register Control
The AD9773 serial port is a flexible, synchronous serial
communications port allowing easy interface to many
industry standard microcontrollers and microprocessors.
The serial I/O is compatible with most synchronous
transfer formats, including both the Motorola SPI and
Intel SSR protocols. The interface allows read/write
access to all registers that configure the AD9773. Single
or multiple byte transfers are supported as well as MSB
first or LSB first transfer formats. The AD9773
’
s serial
interface port can be configured as a single pin I/O
(SDIO) or two unidirectional pins for in/out (SDIO/
SDO).
General Operation of the Serial Interface
There are two phases to a communication cycle with
the AD9773. Phase 1 is the instruction cycle, which is
the writing of an instruction byte into the AD9773,
coincident with the first eight SCLK rising edges. The
instruction byte provides the AD9773 serial port con-
troller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the up-
coming data transfer is read or write, the number of
bytes in the data transfer and the starting register ad-
dress for the first byte of the data transfer. The first
eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the
AD9773.
A logic high on the CS pin, followed by a logic low,
will reset the SPI port timing to the initial state of the
instruction cycle. This is true regardless of the present
state of the internal registers or the other signal levels
present at the inputs to the SPI port. If the SPI port is
in the midst of an instruction cycle or a data transfer
cycle, none of the present data will be written.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9773 and the system controller. Phase 2
of the communication cycle is a transfer of 1, 2, 3, or 4
data bytes as determined by the instruction byte. Nor-
mally, using one multibyte transfer is the preferred
method. However, single byte data transfers are useful to
reduce CPU overhead when register access requires one
byte only. Registers change
immediately
upon writing to the
last bit of each transfer byte.
Instruction Byte
The instruction byte contains the following information
as shown below:
Figure 3. AD9773 SPI Port Interface
R/W
- bit 7 of the instruction byte determines whether a
read or a write data transfer will occur after the instruction
byte write. Logic high indicates read operation . Logic
zero indicates a write operation. N1, N0 -Bits 6 and 5 of
the instruction byte determine the number of bytes to be
transferred during the data transfer cycle. The bit decodes
are shown in the following table:
A4, A3, A2, A1, A0
—
Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9773.
Serial Interface Port Pin Description
SCLK (pin55) - Serial Clock
. The serial clock pin is used
to synchronize data to and from the AD9773 and to run
the internal state machines. SCLK maximum frequency
is 15 MHz. All data input to the AD9773 is registered on
the rising edge of SCLK. All data is driven out of the
AD9773 on the falling edge of SCLK.
CSB (pin 56) - Chip Select
. Active low input starts and
gates a communication cycle. It allows more than one
device to be used on the same serial communications
lines. The SDO and SDIO pins will go to a high
impedance state when this input is high. Chip select
should stay low during the entire communication cycle.
SDIO (pin 54) - Serial Data I/O
. Data is always written
into the AD9773 on this pin. However, this pin can be
used as a bidirectional data line. The configuration of this
pin is controlled by Bit 7 of register address 00h. The
default is logic zero, which configures the SDIO pin as
unidirectional.
SDO(pin 53) - Serial Data Out
. Data is read from this pin
for protocols that use separate lines for transmitting and
receiving data. In the case where the AD9773 operates in
a single bidirectional I/O mode, this pin does not output
data and is set to a high impedance state.
MSB/LSB Transfers
The AD9773 serial port can support both most signifi-
cant bit (MSB) first or least significant bit (LSB) first
data formats. This functionality is controlled by register
address 00h bit 6. The default is MSB first. When this bit
is set active high, the AD9773 serial port is in LSB first
AD9773 SPI Port
Interface
SCLK (pin 55)
CSB (pin 56)
SDIO (pin 54)
SDO (pin 53)
REV. PrA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9773-EB | 制造商:Analog Devices 功能描述: |
| AD9773-EBZ | 功能描述:BOARD EVALUATION AD9773 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9774 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters |
| AD9774AS | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:14-BIT 32 MSPS TXDAC W/4X INTERPOLATION - Bulk 制造商:Analog Devices 功能描述:14BIT DAC CMOS SMD 9774 LQFP44 |
| AD9774ASRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:14-BIT 32 MSPS TXDAC W/4X INTERPOLATION - Bulk |
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