參數(shù)資料
型號: AD9773EB
廠商: Analog Devices, Inc.
英文描述: 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter
中文描述: 12位,160 MSPS的2】/ 4】/ 8】TxDAC系列插雙D / A轉(zhuǎn)換
文件頁數(shù): 12/19頁
文件大?。?/td> 218K
代理商: AD9773EB
AD9773
Address 03h
Bit 1,0
12
PRELIMINARY TECHNICAL DATA
Setting this divide ratio to a higher number allows the VCO in the PLL to run at a high rate (for
best performance) while the DAC input and output clocks run substantially slower. The
divider ratio is set according to the following table:
00
01
10
11
÷
1
÷
2
÷
4
÷
8
Address 04h
Bit 7
Logic 0 (default) disables the internal PLL. Logic 1 enables the PLL.
Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump
bias current is controlled by the divider ratio defined in address 3h, bits 1 and 0. Logic 1
allows the user to manually define the charge pump bias current using address 4h, bits 2, 1
and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling
performance of the PLL.
With the charge pump control set to manual, these bits define the charge pump bias current
according to the following table:
000
50
μ
amps
001
100
010
200
011
400
100
800
Bit 6
Bit 2,1,0
Address 05h,09h
Bits 7-0 These bits represent an 8 bit binary number (bit 7, MSB) which defines the fine gain
adjustment of the I (5h) and Q (9h) DAC according to the equation given below.
Bits 3-0 These bits represent a 4 bit binary number (bit 3, MSB) which defines the coarse
gain adjustment of the I (6h) and Q (Ah) DACs according to the equation below.
Bits 7-0
Bit 1,0
The ten bits from these two address pairs (7h,8h and Bh,Ch) represent a 10 bit
binary number which defines the offset adjustment of the I and Q DACs according to
the equation below (7h,Bh - bit 7 MSB / 8h,Ch - bit 0 LSB)
Bit 7
This bit determines the direction of the offset of the I (8h) and Q (Ch) DACs. A logic
0 will apply a positive offset current to I
, while a logic 1 will apply a positive
offset current to I
. The magnitude of the offset current is defined by the bits in
addresses 7h,Bh,8h,Ch according the the formulas given below.
Address 06h,0Ah
Address 07h,0Bh
Address 08h,0Ch
Address 08h,0Ch
Figure 2. I
OUTA
and I
OUTB
as a function of fine gain, coarse gain and offset adjustment.
*Note that I
is different for the one resistor and two resistor (1R,2R) modes. See the
description for 1R/2R mode control on page 11 (address 0h, bit 2) for the value I
REF
of in
either mode.
×
3
+
6
=
16
REF
REF
8
OUTA
2
data
24
1024
256
fine
32
I
16
1
coarse
I
I
×
3
+
6
=
16
16
REF
REF
8
OUTB
2
1
data
-
2
24
1024
256
fine
32
I
16
1
coarse
I
I
(1R Mode)
(2R Mode)
×
=
1024
OFFSET
I
4
I
REF
OFFSET
×
=
1024
OFFSET
I
2
I
REF
OFFSET
REV. PrA
相關(guān)PDF資料
PDF描述
AD9774AS 14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
AD9774EB 14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
AD9774 14-Bit,32 MSPS DAC with 4× Interpolation Filters(14位的,輸入數(shù)據(jù)數(shù)率為32MSPS的具有內(nèi)插濾波器的D/A轉(zhuǎn)換器)
AD9775 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
AD9775BSV 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9773-EB 制造商:Analog Devices 功能描述:
AD9773-EBZ 功能描述:BOARD EVALUATION AD9773 RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率(每秒):- 數(shù)據(jù)接口:串行,SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9774 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
AD9774AS 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:14-BIT 32 MSPS TXDAC W/4X INTERPOLATION - Bulk 制造商:Analog Devices 功能描述:14BIT DAC CMOS SMD 9774 LQFP44
AD9774ASRL 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:14-BIT 32 MSPS TXDAC W/4X INTERPOLATION - Bulk