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參數(shù)資料
| 型號： | AD9755-EB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9755 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 300M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 11ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9755 |
| 相關(guān)產(chǎn)品： | AD9755ASTZRL-ND - IC DAC 14BIT 300MSPS 48-LQFP AD9755ASTZ-ND - IC DAC 14BIT 300MSPS 48-LQFP |
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REV. B
AD9755
–13–
NONINTERLEAVED MODE WITH PLL DISABLED
If the data at only one port is required, the AD9755 interface
can operate as a simple double buffered latch with no interleaving.
On the rising edge of the 1
× clock, input latch 1 or 2 is updated
with the present input data (depending on the state of DIV0/
DIV1). On the next rising edge, the DAC latch is updated and a
time tPD later, the DAC output reflects this change. Figure 13
represents the AD9755 timing in this mode.
tH
tS
tLPW
tPD
DATA OUT
PORT 1 OR
PORT 2
1
CLOCK
IOUTA OR IOUTB
XX
DATA IN
PORT 1 OR
PORT 2
Figure 13. Timing Requirements, Noninterleaved Mode
with PLL Disabled
DAC TRANSFER FUNCTION
The AD9755 provides complementary current outputs, IOUTA and
IOUTB. IOUTA provides a near full-scale current output, IOUTFS,
when all bits are high (i.e., DAC CODE = 16383) while IOUTB,
the complementary output, provides no current. The current
output appearing at IOUTA and IOUTB is a function of both the
input code and IOUTFS, and can be expressed as
I
DAC CODE
I
OUTA
OUTFS
=
() ×
16383
(1)
I
DAC CODE
I
OUTB
OUTFS
=
()
×
16383
16384
(2)
where DAC CODE = 0 to 16383 (i.e., decimal representation).
As mentioned previously, IOUTFS is a function of the reference
current, IREF, which is nominally set by a reference voltage,
VREFIO, and external resistor RSET. It can be expressed as
II
OUTFS
REF
=×
32
(3)
where IV
R
REF
REFIO
SET
=
(4)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
should be directly connected to matching resistive loads, RLOAD,
that are tied to analog common, ACOM. Note that RLOAD may
represent the equivalent load resistance seen by IOUTA or IOUTB
as would be the case in a doubly terminated 50
or 75 cable.
The single-ended voltage output appearing at the IOUTA and
IOUTB nodes is simply
VI
R
OUTA
LOAD
=×
(5)
VI
R
OUTB
LOAD
=×
(6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain specified
distortion and linearity performance.
VI
I
R
DIFF
OUTA
OUTB
LOAD
=
() ×
(7)
Substituting the values of IOUTA, IOUTB, and IREF, VDIFF can be
expressed as
V
DAC CODE
RR
V
DIFF
LOAD
SET
REFIO
=
()
{}×
() ×
2
16383 16384
32
(8)
INTERLEAVED (2 ) MODE WITH PLL DISABLED
The relationship between the internal and external clocks in this
mode is shown in Figure 11. A clock at the output update data
rate (2
× the input data rate) must be applied to the CLK inputs.
Internal dividers then create the internal 1
× clock necessary for
the input latches. Although the input latches are updated on the
rising edge of the delayed internal 1
× clock, the setup-and-hold
times given in the Digital Specifications table are with respect to
the rising edge of the external 2
× clock. With the PLL disabled,
a load-dependent delayed version of the 1
× clock is present at
the PLLLOCK pin. This signal can be used to synchronize the
external data.
PORT 1
DATA X
DATA Y
tH
tS
tLPW
tPD
DATA X
DATA Y
PORT 2
IOUTA OR IOUTB
DELAYED
INTERNAL
1
CLK
DATA IN
tPD
tD
DATA ENTERS
INPUT LATCHES
ON THIS EDGE
EXTERNAL
2
CLK
EXTERNAL
1
CLK
@ PLLLOCK
Figure 11. Timing Requirements, Interleaved (2
×) Mode
with PLL Disabled
Updates to the data at input Ports 1 and 2 should be synchro-
nized to the specific rising edge of the external 2
× clock that
corresponds to the rising edge of the 1
× internal clock, as shown
in Figure 11. To ensure synchronization, a Logic 1 must be
momentarily applied to the RESET pin. Doing this and return-
ing RESET to Logic 0 brings the 1
× clock at PLLLOCK to a
Logic 1. On the next rising edge of the 2
× clock, the 1× clock
will go to Logic 0. On the second rising edge of the 2
× clock, the
1
× clock (PLLLOCK) will again go to Logic 1, as well as update
the data in both of the input latches. The details of this are
shown in Figure 12.
RESET
PLLLOCK
EXTERNAL
2
CLOCK
tRH = 1.2ns
tRS = 0.2ns
DATA ENTERS
INPUT LATCHES
ON THESE EDGES
Figure 12. Reset Function Timing with PLL Disabled
For proper synchronization, sufficient delay must be present
between the time RESET goes low and the rising edge of the 2
×
clock. RESET going low must occur either at least tRS ns before
the rising edge of the 2
× clock, or t
RH ns afterwards. In the first
case, the immediately occurring CLK rising edge will cause
PLLLOCK to go low. In the second case, the next CLK rising
edge will toggle PLLLOCK.
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