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參數(shù)資料
| 型號(hào)： | AD9755-EB |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9755 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 300M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 11ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9755 |
| 相關(guān)產(chǎn)品： | AD9755ASTZRL-ND - IC DAC 14BIT 300MSPS 48-LQFP AD9755ASTZ-ND - IC DAC 14BIT 300MSPS 48-LQFP |
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REV. B
AD9755
–11–
PORT 1
DATA X
DATA Y
tH
tS
tLPW
tPD
DATA X
DATA Y
1/2 CYCLE +
tPD
PORT 2
IOUTA OR IOUTB
CLK
DATA IN
Figure 7a. DAC Input Timing Requirements
with PLL Active, Single Clock Cycle
PORT 1
DATA X
DATA Z
DATA X
DATA Y
PORT 2
IOUTA OR IOUTB
CLK
DATA IN
DATA Z
DATA W
XXX
DATA W
DATA Y
Figure 7b. DAC Input Timing Requirements
with PLL Active, Multiple Clock Cycles
Typically, the VCO can generate outputs of 100 MHz to 400 MHz.
The range control is used to keep the VCO operating within its
designed range while allowing input clocks as low as 6.25 MHz.
With the PLL active, logic levels at DIV0 and DIV1 determine
the divide (prescaler) ratio of the range controller. Table I gives
the frequency range of the input clock for the different states of
DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels with PLL Active
CLK Frequency
DIV1
DIV0
Range Controller
50 MHz–150 MHz
0
÷1
25 MHz–100 MHz
0
1
÷2
12.5 MHz–50 MHz
1
0
÷4
6.25 MHz–25 MHz
1
÷8
A 392
resistor and 1.0 F capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise versus
settling/acquisition time characteristics of the PLL. To obtain
optimum noise and distortion performance, PLLVDD should be
set to a voltage level similar to DVDD and CLKVDD.
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its
maximum output frequency of 400 MHz.
As stated earlier, applications requiring input data rates below
6.25 MSPS must disable the PLL clock multiplier and provide
an external 2
× reference clock. At higher data rates however,
applications already containing a low phase noise (i.e., jitter)
reference clock that is twice the input data rate should consider
disabling the PLL clock multiplier to achieve the best SNR
performance from the AD9755. Note that the SFDR performance
of the AD9755 remains unaffected with or without the PLL clock
multiplier enabled.
1.2V REF
AVDD
IREF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
AD9755
REFERENCE
SECTION
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
Figure 4. Internal Reference Configuration
1.2V REF
AVDD
IREF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
AD9755
REFERENCE
SECTION
EXTERNAL
REFERENCE
AVDD
Figure 5. External Reference Configuration
PLL CLOCK MULTIPLIER OPERATION
The Phase-Locked Loop (PLL) is intrinsic to the operation of the
AD9755 in that it produces the necessary internally synchronized
2
× clock for the edge-triggered latches, multiplexer, and DAC.
With PLLVDD connected to its supply voltage, the AD9755 is in
PLL active mode. Figure 6 shows a functional block diagram of
the AD9755 clock control circuitry with PLL active. The
circuitry consists of a phase detector, charge pump, voltage
controlled oscillator (VCO), input data rate range control, clock
logic circuitry, and control input/outputs. The
÷ 2 logic in the
feedback loop allows the PLL to generate the 2
× clock needed for
the DAC output latch.
Figure 7 defines the input and output timing for the AD9755
with the PLL active. CLK in Figure 7 represents the clock that
is generated external to the AD9755. The input data at both
Ports 1 and 2 is latched on the same CLK rising edge. CLK may
be applied as a single ended signal by tying CLK– to mid supply
and applying CLK to CLK+, or as a differential signal applied
to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9755 is in PLL active mode,
PLLLOCK is the output of the internal phase detector. When
locked, the lock output in this mode is Logic 1.
CLKCOM
TO INPUT
LATCHES
CLKVDD
(3.0V TO 3.6V)
PLLLOCK
CHARGE
PUMP
PHASE
DETECTOR
LPF
PLLVDD
VCO
392
1.0 F
3.0V TO
3.6V
RANGE
CONTROL
(
1, 2, 4, 8)
DIV0
DIV1
DIFFERENTIAL-
TO-
SINGLE-ENDED
AMP
2
TO DAC
LATCH
CLK+
CLK–
AD9755
Figure 6. Clock Circuitry with PLL Active
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