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參數(shù)資料
| 型號(hào)： | AD974BRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 16BIT 4CH 200KSPS 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 配用： | EVAL-AD974CB-ND - BOARD EVAL FOR AD974 |
REV. A
AD974
–16–
AC PERFORMANCE
The AD974 is fully specified and tested for dynamic perfor-
mance specifications. The ac parameters are required for signal
processing applications such as speech recognition and spectrum
analysis. These applications require information on the ADC’s
effect on the spectral content of the input signal. Hence, the
parameters for which the AD974 is specified include S/(N+D),
THD and Spurious Free Dynamic Range. These terms are
discussed in greater detail in the following sections.
As a general rule, it is recommended that the results from sev-
eral conversions be averaged to reduce the effects of noise and
thus improve parameters such as S/(N+D) and THD. AC per-
formance can be optimized by operating the ADC at its maxi-
mum sampling rate of 200 kHz and digitally filtering the resulting
bit stream to the desired signal bandwidth. By distributing noise
over a wider frequency range the noise density in the frequency
band of interest can be reduced. For example, if the required
input bandwidth is 50 kHz, the AD974 could be oversampled
by a factor of 4. This would yield a 6 dB improvement in the
effective SNR performance.
FREQUENCY – kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–125
0
1020
30
40
50
607080
90
100
AMPLITUDE
–
dB
5
15
25
3545
55
6575
8595
5280 POINT FFT
fSAMPLE = 200kHz
fIN = 20kHz
SNRD = 86.7dB
THD = 100.7dB
Figure 16. FFT Plot
DC PERFORMANCE
The factory calibration scheme used for the AD974 compen-
sates for bit weight errors that may exist in the capacitor array.
The mismatch in capacitor values is adjusted (using the calibra-
tion coefficients) during a conversion, resulting in excellent dc
linearity performance. Figures 17 and 18, respectively, show
typical INL and DNL plots for the AD974 at +25
°C.
A histogram test is a statistical method for deriving an A/D
converter’s differential nonlinearity. A ramp input is sampled
by the ADC and a large number of conversions are taken at
each voltage level, averaged and then stored. The effect of
averaging is to reduce the transition noise by 1/n. If 64 samples
are averaged at each point, the effect of transition noise is
reduced by a factor of 8; i.e., a transition noise of 0.8 LSBs rms
is reduced to 0.1 LSBs rms. Theoretically the codes, during a
test of DNL, would all be the same size and therefore have an
equal number of occurrences. A code with an average number
of occurrences would have a DNL of “0.” A code that is
different from the average would have a DNL that was either
greater or less than zero LSB. A DNL of –1 LSB indicates that
there is a missing code present at the 16-bit level and that the
ADC exhibits 15-bit performance.
SAMPLES – K
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
5
10
15
20
25
30
35
40
45
50
55
60
66
100%
Figure 17. INL Plot
SAMPLES – K
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
5
10
15
20
25
30
35
40
45
50
55
60
66
100%
Figure 18. DNL Plot
INPUT SIGNAL FREQUENCY – kHz
90
1
1000
100
10
80
70
60
50
40
30
20
10
SNR+D (dB) FOR AD974
SINAD
(dB)
FOR
V
IN
=
0dB
Figure 19. S/(N+D) vs. Input Frequency
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