- 您現在的位置：買賣IC網 > PDF目錄10534 > AD9608BCPZ-105 (Analog Devices Inc)IC ADC DUAL 10BIT 64-LFCSP PDF資料下載
參數資料
| 型號： | AD9608BCPZ-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 20/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 10BIT 64-LFCSP |
| 標準包裝： | 1 |
| 位數： | 10 |
| 采樣率（每秒）： | 105M |
| 數據接口： | LVDS，并聯，串行，SPI |
| 轉換器數目： | 2 |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 4 個單端，2 個差分 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
AD9608
Rev. 0 | Page 27 of 40
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
100
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
0997
7-
06
1
Figure 55. Differential PECL Sample Clock (Up to 1 GHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 56. The AD9510/
clock drivers offer excellent jitter performance.
100
0.1F
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
09977-
062
Figure 56. Differential LVDS Sample Clock (Up to 1 GHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
OPTIONAL
100
0.1F
501
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
09
977
-063
Figure 57. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9608 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9608 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow
the clock divider to be resynchronized on every SYNC signal
or only on the first SYNC signal after the register is written.
A valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. A ±5% tolerance is commonly
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9608 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9608. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 58.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
40
45
50
55
60
65
70
35
40
45
50
55
60
65
S
NR
(
d
BF
s)
POSITIVE DUTY CYCLE (%)
DCS ON
DCS OFF
09977
-036
Figure 58. SNR vs. DCS On/Off
相關PDF資料 |
PDF描述 |
|---|---|
| VI-BTK-IV-F2 | CONVERTER MOD DC/DC 40V 150W |
| LTC1278-5CSW#PBF | IC A/DCONV SAMPLNG W/SHTDN24SOIC |
| LTC1278-5CSW | IC A/DCONV SAMPLNG W/SHTDN24SOIC |
| VI-BTJ-IV-F4 | CONVERTER MOD DC/DC 36V 150W |
| AD7777ARZ | IC ADC 10BIT 4CH HS 28SOIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9608BCPZ-125 | 功能描述:IC ADC DUAL 10BIT 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率（每秒）:20M 數據接口:并聯 轉換器數目:2 功率耗散（最大）:155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數目和類型:4 個單端，單極；2 個差分，單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9608BCPZRL7-105 | 功能描述:IC ADC 10BIT 105MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9608BCPZRL7-125 | 功能描述:IC ADC 10BIT 125MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD9609 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS 1.8 V Analog-to-Digital Converter |
| AD9609-20EBZ | 功能描述:BOARD EVALUATION AD9609 20MSPS RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率（每秒）:94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。