參數(shù)資料
型號： AD9558BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 91/104頁
文件大?。?/td> 0K
描述： IC CLOCK TRANSLATOR 64LFCSP
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
標準包裝： 1
類型： 時鐘/頻率轉換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 4:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Data Sheet
AD9558
Rev. B | Page 87 of 104
DPLL PROFILE REGISTERS (REGISTER 0x0700 TO REGISTER 0x07E6)
Note that the default values of the REFA and REFC profiles are as follows: input frequency=19.44 MHz, output frequency = 622.08 MHz/
155.52 MHz, loop bandwidth = 400 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%.
The default values of the REFB and REFD profiles are as follows: input frequency = 8 kHz, output frequency = 622.08 MHz/155.52 MHz,
loop bandwidth = 100 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%.
REFA Profile (Register 0x0700 to Register 0x0726)
Table 78. Reference Period—REFA Profile
Address
Bits
Bit Name
Description
0x0700
[7:0]
Nominal reference period (fs)
Nominal reference period bits[7:0] (default: 0xC9).
0x0701
[7:0]
Nominal reference period bits[15:8] (default: 0xEA).
0x0702
[7:0]
Nominal reference period bits[23:16] (default: 0x10).
0x0703
[7:0]
Nominal reference period bits[31:24] (default: 0x03).
0x0704
[7:0]
Nominal reference period bits[39:32] (default: 0x00).
Default for Register 0x0700 to Register 0x0704 = 0x000310EAC9 = 51.44 ns (1/19.44 MHz).
Table 79. Reference Period Tolerance—REFA Profile
Address
Bits
Bit Name
Description
0x0705
[7:0]
Inner tolerance
Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14).
0x0706
[7:0]
Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00).
0x0707
[7:4]
Reserved
Default: 0x0.
[3:0]
Inner tolerance
Input reference frequency monitor inner tolerance, Bits[19:16].
Default for Register 0x0705 to Register 0x707 = 0x000014 = 20 (5% or 50,000 ppm).
The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of
±12 ppm; an SMC clock requires an outer tolerance of ±48 ppm.
The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (1 ppm).
The tolerance of the input frequency monitor is only as accurate as the system clock
frequency.
0x0708
[7:0]
Outer tolerance
Input reference frequency monitor outer tolerance, Bits[7:0] (default: 0x0A).
0x0709
[7:0]
Input reference frequency monitor outer tolerance, Bits[15:8] (default: 0x00).
0x070A
[7:4]
Reserved
Reserved.
[3:0]
Outer tolerance
Input reference frequency monitor outer tolerance, Bits[19:16].
Default for Register 0x0708 to Register 0x70A = 0x00000A = 10 (10% or 100,000 ppm).
The Stratum 3 clock requires an inner tolerance of ±9.2 ppm and outer tolerance of
±12 ppm; an SMC clock requires outer tolerance of ±48 ppm.
The outer tolerance register setting should always be smaller than the inner tolerance.
Table 80. Reference Validation Timer—REFA Profile
Address
Bits
Bit Name
Description
0x070B
[7:0]
Validation timer (ms)
Validation timer, Bits[7:0] (default: 0x0A).
This is the amount of time a reference input must be valid before it is declared valid by
the reference input monitor (default: 10 ms).
0x070C
[7:0]
Validation timer, Bits[15:8] (default: 0x00).
Table 81. Reserved Register
Address
Bits
Bit Name
Description
0x070D
[7:0]
Reserved
Reserved. Default: 0x00.
Table 82. DPLL Base Loop Filter Selection—REFA Profile
Address
Bits
Bit Name
Description
0x070E
[7:1]
Reserved
Reserved. Default: 0x00.
0
Sel high PM base loop filter
0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high (88.5°) phase margin.
(≤0.1 dB peaking in the closed-loop transfer function for loop BWs ≤ 2 kHz. Setting this
bit is also recommended for loop BW > 2kHz.)
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