參數(shù)資料
型號(hào)： AD9558BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 77/104頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK TRANSLATOR 64LFCSP
產(chǎn)品變化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率轉(zhuǎn)換器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，HSTL，LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 4:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.25GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9558
Data Sheet
Rev. B | Page 74 of 104
GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214)
Multifunction Pin Control (M0 to M7) and IRQ Pin Control (Register 0x0200 to Register 0x0209)
Note that the default setting for the M0 to M5 multifunction pins and the IRQ is that of a 3-level logic input; M6 and M7 are unused inputs at
startup. After startup, M0 to M7 are 2-level inputs or 2-level outputs, based on the settings of Register 0x0200 to Register 0x0208. Setting
Bit 0 in Register 0x0200 to 1 enables M0 to M7 pin functionality.
Table 46. Multifunction Pin (M0 to M7) Control
Address
Bits
Bit Name
Description
0x0200
[7:1]
Reserved
Reserved.
0
Enable M pins and IRQ pin
function
0 (default) = disables the function of the M pins and IRQ pin control register (Address
0x0201 to Address 0x0209) and the M pins and IRQ pin are in 3-level logic input state.
1 = the M pins and IRQ pin are out of 3-level logic input state. Enables the function of the
M pins and IRQ pin control register (Address 0x0201 to Address 0x0209).
0x0201
7
M0 output/
A
input
E
In/out control for M0 pin.
0 = input (2-level logic control pin).
1 (default) = output (2-level logic status pin).
[6:0]
M0 function
See Table 129 and Table 130. Default: 0xB0 = REFA valid.
0x0202
7
M1 output/
A
input
E
In/out control for M1 pin (same as M0).
[6:0]
M1 function
See Table 129 and Table 130. Default: 0xB1 = REFB valid.
0x0203
7
M2 output/
A
input
E
In/out control for M2 pin (same as M0).
[6:0]
M2 function
See Table 129 and Table 130. Default: 0xC0 = REFA active.
0x0204
7
M3 output/
A
input
E
In/out control for M3 pin (same as M0).
[6:0]
M3 function
See Table 129 and Table 130. Default: 0xC1 = REFB active.
0x0205
7
M4 output/
A
input
E
In/out control for M3 pin (same as M0).
[6:0]
M4 function
See Table 129 and Table 130. Default: 0xB2 = REFC valid.
0x0206
7
M5 output/
A
input
E
In/out control for M3 pin (same as M0).
[6:0]
M5 function
See Table 129 and Table 130. Default: 0xB3 = REFD valid.
0x0207
7
M6 output/
A
input
E
In/out control for M3 pin (same as M0).
[6:0]
M6 function
See Table 129 and Table 130. Default: 0xC2 = REFC active.
0x0208
7
M7 output/
A
input
E
In/out control for M3 pin (same as M0).
[6:0]
M7 function
See Table 129 and Table 130. Default: 0xC3 = REFD active.
Table 47. IRQ Pin Output Mode
Address
Bits
Bit Name
Description
0x0209
[7:5]
Reserved
Default: 000b
[4:3]
Status signal at IRQ pin
This selection is valid only when Address 0x0209[2] = 1
00 = DPLL phase locked
01 = DPLL frequency locked
10 = system clock PLL locked
11 (default) = (DPLL phase locked) AND (system clock PLL locked) AND (APLL locked)
2
Use IRQ pin for status signal
0 = uses IRQ pin to monitor IRQ event
1 (default) = uses IRQ pin to monitor internal status signals
[1:0]
IRQ pin driver type
Select the output mode of the IRQ pin
00 = NMOS, open drain (requires an external pull-up resistor)
01 = PMOS, open drain (requires an external pull-down resistor)
10 = CMOS, active high
11 (default) = CMOS, active low
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