參數(shù)資料
型號: AD9524/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 17/56頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9524
設計資源: AD9524 Schematic
AD9524 BOM
AD9524 Gerber Files
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9524
主要屬性: USB 供電或外部電源
次要屬性: 狀態(tài) LED
已供物品:
配用: AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
AD9524
Data Sheet
Rev. E | Page 24 of 56
Clock Distribution Synchronization
A block diagram of the clock distribution synchronization
functionality is shown in Figure 27. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
Direct synchronization source via the sync dividers bit (see
Register 0x232, Bit 0 in Table 56)
Device pin, SYNC (Pin 13)
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part.
FAN OUT
VCO OUTPUT DIVIDER
SYNC (PIN 13)
SYNC
DIVIDER
DRIVER
OUTx
OUT
SYNC
PHASE
DIVIDE
SYNC DIVIDERS BIT
09081-
025
Figure 27. Clock Output Synchronization Block Diagram
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
VCO DIVIDER OUTPUT CLOCK
SYNC
CONTROL
6 × 0.5 PERIODS
0
84
39-
0
26
Figure 28. Clock Output Synchronization Timing Diagram
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