參數(shù)資料
型號(hào)： AD9523-1BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 19/60頁
文件大?。?/td> 0K
描述： IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準(zhǔn)包裝： 400
類型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，光纖通道，SONET/SDH
輸入： CMOS
輸出： HSTL，LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1GHz
電源電壓： 1.768 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 帶卷 (TR)
配用： AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
AD9523-1
Rev. B | Page 26 of 60
Clock Distribution Synchronization
first sets and then clears the bit. The synchronization event is the
clearing operation (that is, the Logic 1 to Logic 0 transition of
the bit). The dividers are all automatically synchronized to each
other when PLL2 is ready. The dividers support programmable
phase offsets from 0 to 63 steps, in half periods of the input
clock (for example, the VCO divider output clock). The phase
offsets are incorporated into the dividers through a preset for the
first output clock period of each divider. Phase offsets are
supported only by programming the initial phase and divide
value and then issuing a sync to the distribution (automatically
at startup or manually, if desired).
A block diagram of the clock distribution synchronization
functionality is shown in Figure 29. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
Direct synchronization source via the sync dividers bit
(see Table 55, Register 0x232, Bit 0)
Device pin, SYNC (Pin 17)
In normal operation, the phase offsets are already programmed
through the EEPROM or the SPI/I2C port before the AD9523-1
starts to provide outputs. Although the user cannot adjust the
phase offsets while the dividers are operating, it is possible to
adjust the phase of all the outputs together without powering
down PLL1 and PLL2. This is accomplished by programming
the new phase offset, using Bits[7:2] in Register 0x192 (see
Table 51) and then issuing a divide sync signal by using the
SYNC pin or the sync dividers bit (Register 0x232, Bit 0).
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part.
Both sources of the primary synchronization signal are logic OR’d;
therefore, any one of them can synchronize the clock distribution
output at any time. When using the sync dividers bit, the user
FAN OUT
VCO OUTPUT DIVIDER
SYNC (PIN 17)
SYNC
SYNC DIVIDERS BIT
DIVIDER
DRIVER
OUTx
OUT
SYNC
PHASE
DIVIDE
0
9278-
025
Figure 29. Clock Distribution Synchronization Block Diagram
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
VCO DIVIDER OUTPUT CLOCK
SYNC
CONTROL
6 × 0.5 PERIODS
09278-
026
Figure 30. Clock Output Synchronization Timing Diagram
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AD9524 制造商:AD 制造商全稱:Analog Devices 功能描述:Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs
AD9524/PCBZ 功能描述:BOARD EVAL FOR AD9524 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9524BCPZ 功能描述:IC INTEGER-N CLCK GEN 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
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