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參數(shù)資料
| 型號： | AD9520-5BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 70/76頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64-LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9520-5
Data Sheet
Rev. A | Page 72 of 76
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9520 provide the lowest jitter
clock signals available from the AD9520. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 42 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 59) or Y-termination (see Figure 60) is recommended.
In both cases, VS of the receiving buffer should match VS_DRV. If it
does not, ac coupling is recommended (see Figure 61).
Figure 59. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
Figure 60. DC-Coupled 3.3 V LVPECL Y-Termination
Figure 61. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-Termination
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
where VS_DRV = 2.5 V, the 50 termination resistor connected to
ground in Figure 60 should be changed to 19 .
Far-End Thevenin Termination
Far-end Thevenin termination uses a resistor network to
provide 50 termination to a dc voltage that is below VOL of
equal VS of the receiving buffer. Although the resistor combination
shown results in a dc bias point of VS_DRV 2 V, the actual
common-mode voltage is VS_DRV 1.3 V because there is
additional current flowing from the AD9520 LVPECL driver
through the pull-down resistor.
The circuit is identical for the case where VS_DRV = 2.5 V, except that
the pull-down resistor is 62.5 and the pull-up resistor is 250 .
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9520 can be configured as CMOS
drivers. When selected as a CMOS driver, each output becomes
a pair of CMOS outputs, each of which can be individually
turned on or off and set as inverting or noninverting. These
outputs are 3.3 V or 2.5 V CMOS compatible. However, every
output driver (including the LVPECL drivers) must be run at
either 2.5 V or 3.3 V. The user cannot mix and match 2.5 V and
3.3 V outputs.
When using single-ended CMOS clocking, consider the
following guidelines:
Using the CMOS drivers in the same output channel group
as the LVPECL drivers may result in performance
degradation of the LVPECL drivers. Where possible,
program the two CMOS drivers that form the same output
of a differential pair to be out of phase such that one driver
is high while the other is low. It is recommended that the
evaluation board be used to verify the performance of the
AD9520 in demanding applications where both CMOS and
LVPECL drivers are in the same group, and the very best
jitter performance is required.
If possible, design point-to-point connections such that
each driver has only one receiver. Connecting outputs in
this manner allows for simple termination schemes and
minimizes ringing due to possible mismatched impedances
on the output trace. Series termination at the source is
generally required to provide transmission line matching
and/or to reduce current transients at the driver.
The value of the resistor is dependent on the board design
and timing requirements (typically 10 to 100 is used).
CMOS outputs are also limited in terms of the capacitive
load or trace length that they can drive. Typically, trace
lengths of less than 3 inches are recommended to preserve
signal rise/fall times and signal integrity.
Figure 62. Series Termination of CMOS Output
VS_DRV
LVPECL
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
07239-
045
VS_DRV
LVPECL
Z0 = 50
VS = VS_DRV
LVPECL
50
Z0 = 50
07239-
047
VS_DRV
LVPECL
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
07239-
046
CMOS
10
60.4
(1.0 INCH)
MICROSTRIP
07239-
076
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9520-5BCPZ-REEL7 | 功能描述:IC CLOCK GEN EXT VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521KH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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