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| 型號： | AD9520-4/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/80頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9520-4 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9520-4 |
| 主要屬性： | 1.4 ~ 1.8 GHz 輸出頻率 |
| 次要屬性： | 接受 CMOS、LVDS 或者最高 250 MHz 的 LVPECL 基準(zhǔn) |
| 已供物品： | 板 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9520-4BCPZ-REEL7-ND - IC CLOCK GEN 1.6GHZ VCO 64LFCSP AD9520-4BCPZ-ND - IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
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Data Sheet
AD9520-4
Rev. A | Page 49 of 80
LVPECL Output Drivers
The LVPECL differential voltage (VOD) is selectable (from
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB). The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be set to either 2.5 V or 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
R2
200
R1
200
SW1B
SW1A
SW2
QN2
QN1
N2
N1
OUT
4.4mA
07217-
058
Figure 54. LVPECL Output Simplified Equivalent Circuit
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that causes a dc voltage to
appear at the powered down outputs. However, total power-
down mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting Register 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while powered
down. There are three ways to activate safe power-down mode:
individually set the power-down bit for each driver, power down an
individual output channel (all of the drivers associated with that
channel are powered down automatically), and activate sleep mode.
CMOS Output Drivers
The user can also individually configure each LVPECL output as a
pair of CMOS outputs, which provides up to 24 CMOS outputs.
When an output is configured as CMOS, CMOS Output A and
CMOS Output B are automatically turned on. For any given
differential pair, either CMOS Output A or CMOS Output B
can be turned on or off independently.
The user can also select the relative polarity of the CMOS outputs
for any combination of inverting and noninverting (refer to
Register 0x0F0 to Register 0x0FB).
OUT1/
OUT1
VS_DRV
07217-
035
Figure 55. CMOS Equivalent Output Circuit
Each CMOS output can be powered down, as needed, to save
power. The CMOS output power-down is individually controlled
by the enable CMOS output bits, Bits[6:5] in Register 0x0F0
to Register 0x0FB. The CMOS driver is in tristate when it is
powered down.
Note that activating a CMOS driver in the same output channel
group as the LVPECL drivers may cause the LVPECL driver
performance to degrade. In applications where jitter performance
is critical, the user should test the desired configuration using
an evaluation board, and special steps may need to be taken to
ensure the desired performance.
RESET MODES
The AD9520 has a power-on reset (POR) and several other
ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when VS
reaches ~2.6 V (<2.8 V) and restores the chip either to the setting
that is stored in the EEPROM (with the EEPROM pin = 1b) or
to the on-chip setting (with the EEPROM pin = 0b). At power-on,
the AD9520 also executes a SYNC operation approximately 50 ms
after the supply reaches ~2.4 V, which brings the outputs into phase
alignment according to the default settings. It takes ~70 ms for
the outputs to begin toggling after the power-on reset pulse
signal is internally generated.
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| AD9520-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
| AD9520-5/PCBZ | 功能描述:BOARD EVAL FOR AD9520-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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