- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9157 > AD9510BCPZ (Analog Devices Inc)IC CLOCK DIST 8OUT PLL 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9510BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DIST 8OUT PLL 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出緩沖器（分配），除法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.2GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 配用： | AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510 AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Data Sheet
AD9510
Rev. B | Page 29 of 56
VCO/VCXO Feedback Divider—N (P, A, B)
The N divider is a combination of a prescaler, P (3 bits), and two
counters, A (6 bits) and B (13 bits). Although the PLL of the
prescaler that allows lower values of N. The prescaler has both
a dual modulus (DM) and a fixed divide (FD) mode. The AD9510
prescaler modes are shown in Table 15.
Table 15. PLL Prescaler Modes
Mode
(FD = Fixed Divide,
DM = Dual Modulus)
Value in
Register 0x0A[4:2]
Divide By
FD
000
1
FD
001
2
P = 2 DM
010
P/P + 1 = 2/3
P = 4 DM
011
P/P + 1 = 4/5
P = 8 DM
100
P/P + 1 = 8/9
P = 16 DM
101
P/P + 1 = 16/17
P = 32 DM
110
P/P + 1 = 32/33
FD
111
3
When using the prescaler in FD mode, the A counter is not
used, and the B counter may need to be bypassed. The DM
prescaler modes set some upper limits on the frequency, which
can be applied to CLK2. See Table 16.
Table 16. Frequency Limits of Each Prescaler Mode
A and B Counters
The AD9510 B counter has a bypass mode (B = 1), which is not
available on the ADF4106. The B counter bypass mode is valid
only when using the prescaler in FD mode. The B counter is
bypassed by writing 1 to the B counter bypass bit (Register 0x0A[6]
= 1b). The valid range of the B counter is 3 to 8191. The default
after a reset is 0, which is invalid.
Note that the A counter is not used when the prescaler is in
FD mode.
Note also that the A/B counters have their own reset bit, which
is primarily intended for testing. The A and B counters can also
be reset using the shared reset bit of the R, A, and B counters
(Register 0x09[0]).
Determining Values for P, A, B, and R
When operating the AD9510 in a dual-modulus mode, the
input reference frequency, fREF, is related to the VCO output
frequency, fVCO.
fVCO = (fREF/R) × (PB + A) = fREF × N/R
When operating the prescaler in fixed divide mode, the A
counter is not used and the equation simplifies to
fVCO = (fREF/R) × (PB) = fREF × N/R
By using combinations of dual modulus and fixed divide modes,
the AD9510 can achieve values of N all the way down to N = 1.
Table 17 shows how a 10 MHz reference input can be locked to
any integer multiple of N. Note that the same value of N can be
derived in different ways, as illustrated by N = 12.
Table 17. P, A, B, R—Smallest Values for N
fREF
R
P
A
B
N
fVCO
Mode
Notes
10
1
X
1
10
FD
P = 1, B = 1 (Bypassed)
10
1
2
X
1
2
20
FD
P = 2, B = 1 (Bypassed)
10
1
X
3
30
FD
P = 1, B = 3
10
1
X
4
40
FD
P = 1, B = 4
10
1
X
5
50
FD
P = 1, B = 5
10
1
2
X
3
6
60
FD
P = 2, B = 3
10
1
2
0
3
6
60
DM
P/P + 1 = 2/3, A = 0, B = 3
10
1
2
1
3
7
70
DM
P/P + 1 = 2/3, A = 1, B = 3
10
1
2
3
8
80
DM
P/P + 1 = 2/3, A = 2, B = 3
10
1
2
1
4
9
90
DM
P/P + 1 = 2/3, A = 1, B = 4
10
1
2
X
5
10
100
FD
P = 2, B = 5
10
1
2
0
5
10
100
DM
P/P + 1 = 2/3, A = 0, B = 5
10
1
2
1
5
11
110
DM
P/P + 1 = 2/3, A = 1, B = 5
10
1
2
X
6
12
120
FD
P = 2, B = 6
10
1
2
0
6
12
120
DM
P/P + 1 = 2/3, A = 0, B = 6
10
1
4
0
3
12
120
DM
P/P + 1 = 4/5, A = 0, B = 3
10
1
4
1
3
13
130
DM
P/P + 1 = 4/5, A = 1, B = 3
Mode (DM = Dual Modulus)
CLK2
P = 2 DM (2/3)
<600 MHz
P = 4 DM (4/5)
<1000 MHz
P = 8 DM (8/9)
<1600 MHz
P = 16 DM
<1600 MHz
P = 32 DM
<1600 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-BWF-MW-B1 | CONVERTER MOD DC/DC 72V 100W |
| AD9520-5BCPZ | IC CLOCK GEN EXT VCO 64-LFCSP |
| M83723/83G1203N | CONN RCPT 3POS WALL MT W/PINS |
| X9116WM8 | IC DIGITAL POT 10K 16TP 8MSOP |
| MS27467E25F35SD | CONN PLUG 128POS STRAIGHT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9510BCPZ-REEL7 | 功能描述:IC CLOCK DIST 8OUT PLL 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9510-VCO/PCB | 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS)) |
| AD9510-VCO/PCBZ | 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9511 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9511/PCB | 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。