參數(shù)資料
型號： AD9510BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 21/56頁
文件大?。?/td> 0K
描述： IC CLOCK DIST 8OUT PLL 64LFCSP
標準包裝： 1
類型： 扇出緩沖器（分配），除法器
PLL： 是
輸入： 時鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.2GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
配用： AD9510-VCO/PCBZ-ND - BOARD EVALUATION FOR AD9510
AD9510/PCBZ-ND - BOARD EVALUATION FOR AD9510
AD9510
Data Sheet
Rev. B | Page 28 of 56
FUNCTIONAL DESCRIPTION
OVERALL
Figure 33 shows a block diagram of the AD9510. The chip
combines a programmable PLL core with a configurable clock
distribution system. A complete PLL requires the addition of a
suitable external VCO (or VCXO) and loop filter. This PLL can
lock to a reference input signal and produce an output that is
related to the input frequency by the ratio defined by the pro-
grammable R and N dividers. The PLL cleans up some jitter
from the external reference signal, depending on the loop band-
width and the phase noise performance of the VCO (VCXO).
The output from the VCO (VCXO) can be applied to the clock
distribution section of the chip, where it can be divided by any
integer value from 1 to 32. The duty cycle and relative phase of
the outputs can be selected. There are four LVPECL outputs,
(OUT0, OUT1, OUT2, and OUT3) and four outputs that can be
either LVDS or CMOS level outputs (OUT4, OUT5, OUT6, and
OUT7). Two of these outputs (OUT5 and OUT6) can also make
use of a variable delay block.
Alternatively, the clock distribution section can be driven directly
by an external clock signal, and the PLL can be powered off.
Whenever the clock distribution section is used alone, there is
no clock cleanup. The jitter of the input clock signal is passed
along directly to the distribution section and may dominate at
the clock outputs.
PLL SECTION
The AD9510 consists of a PLL section and a distribution section.
If desired, the PLL section can be used separately from the
distribution section.
The AD9510 has a complete PLL core on-chip, requiring only
an external loop filter and VCO/VCXO. This PLL is based on
the ADF4106, a PLL noted for its superb low phase noise per-
formance. The operation of the AD9510 PLL is nearly identical
to that of the ADF4106, offering an advantage to those with
experience with the ADF series of PLLs. Differences include the
addition of differential inputs at REFIN and CLK2, a different
control register architecture. Also, the prescaler is changed to
allow N as low as 1. The AD9510 PLL implements the digital
lock detect feature somewhat differently than the ADF4106
does, offering improved functionality at higher PFD rates. See
PLL Reference Input—REFIN
The REFIN/REFINB pins can be driven by either a differential
or a single-ended signal. These pins are internally self-biased so
that they can be ac-coupled via capacitors. It is possible to dc-
couple to these inputs. If REFIN is driven single-ended, decouple
the unused side (REFINB) via a suitable capacitor to a quiet
ground. Figure 34 shows the equivalent circuit of REFIN.
Figure 34. REFIN Equivalent Circuit
VCO/VCXO Clock Input—CLK2
The CLK2 differential input is used to connect an external
VCO or VCXO to the PLL. Only the CLK2 input port has a
connection to the PLL N divider. This input can receive up to
1.6 GHz. These inputs are internally self-biased and must be
ac-coupled via capacitors.
Alternatively, CLK2 can be used as an input to the distribution
section. This is accomplished by setting Register 0x45[0] = 0b.
The default condition is for CLK1 to feed the distribution section.
Figure 35. CLK1, CLK2 Equivalent Input Circuit
PLL Reference Divider—R
The REFIN/REFINB inputs are routed to reference divider, R,
which is a 14-bit counter. R can be programmed to any value
from 1 to 16383 (a value of 0 results in a divide by 1) via its
control register (Register 0x0B[5:0], Register 0x0C[7:0]). The
output of the R divider goes to one of the phase frequency
detector inputs. Do not exceed the maximum allowable frequency
into the phase frequency detector (PFD). This means that the
REFIN frequency divided by R must be less than the maximum
allowable PFD frequency. See Figure 34.
05046-033
VS
REFIN
REFINB
150
150
10k
12k
10k
10k
05046-016
VS
CLOCK INPUT
STAGE
CLK
CLKB
5k
5k
2.5k
2.5k
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AD9510BCPZ-REEL7 功能描述:IC CLOCK DIST 8OUT PLL 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9510-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE, DIVIDER - Bulk 制造商:Analog Devices 功能描述:IC ((NS))
AD9510-VCO/PCBZ 功能描述:BOARD EVALUATION FOR AD9510 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9511 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9511/PCB 制造商:Analog Devices 功能描述:1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,DIVIDERS, DELAY ADJUST, FIVE OUTPUTS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk
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