AVDD = 1.8 V, DRVDD = 1.8 V, TMIN
參數(shù)資料
型號: AD9484BCPZ-500
廠商: Analog Devices Inc
文件頁數(shù): 18/24頁
文件大?。?/td> 0K
描述: IC ADC 8BIT 500MSPS 56LFCSP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 8
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 720mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
輸入數(shù)目和類型: 1 個差分,雙極
AD9484
Rev. A | Page 3 of 24
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = 40°C, TMAX = +85°C, fIN = 1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table
1.
Parameter1
Temp
Min
Typ
Max
Unit
RESOLUTION
8
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
25°C
0
mV
Full
3.0
+3.0
mV
Gain Error
25°C
1.0
% FS
Full
5.0
+7.0
% FS
Differential Nonlinearity (DNL)
25°C
±0.13
LSB
Full
0.25
+0.25
LSB
Integral Nonlinearity (INL)
25°C
±0.1
LSB
Full
0.15
+0.15
LSB
INTERNAL REFERENCE
VREF
Full
0.71
0.75
0.78
V
TEMPERATURE DRIFT
Offset Error
Full
18
μV/°C
Gain Error
Full
0.07
%/°C
ANALOG INPUTS (VIN+, VIN)
Differential Input Voltage Range2
Full
1.18
1.5
1.6
V p-p
Input Common-Mode Voltage
Full
1.7
V
Input Resistance (Differential)
Full
1
Input Capacitance (Differential)
Full
1.3
pF
POWER SUPPLY
AVDD
Full
1.75
1.8
1.9
V
DRVDD
Full
1.75
1.8
1.9
V
Supply Currents
IAVDD3
Full
283
300
mA
Full
89
100
mA
Power Dissipation
SDR Mode4
Full
670
720
mW
Standby Mode
Full
40
50
mW
Power-Down Mode
Full
2.5
7
mW
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the
section.
3 IAVDD and IDRVDD are measured with a 1 dBFS, 10.3 MHz sine input at a rated sample rate.
4 Single data rate mode; this is the default mode of the AD9484.
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