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參數(shù)資料
| 型號： | AD9433 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| 中文描述： | 12位，105 MSPS/125 MSPS的中頻采樣的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | AD9433 |
REV. 0
AD9433
–15–
Layout Information
The schematic and layout of the evaluation board (Figures 13
–
21)
represents a typical implementation of the AD9433. A multi-
layer board is recommended to achieve best results. It is highly
recommended that high quality, ceramic chip capacitors be used
to decouple each supply pin to ground directly at the device.
The pinout of the AD9433 facilitates ease of use in the implemen-
tation of high frequency, high resolution design practices. All of the
digital outputs and their supply and ground pin connections are
segregated to one side of the package, with the inputs on the
opposite side for isolation purposes.
Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog portion of
the AD9433 (V
CC
, AIN, and VREF), minimal capacitive loading
should be placed on these outputs.
It is recommended that a fan-out of only one gate should be used
for all AD9433 digital outputs.
The layout of the encode circuit is equally critical, and should
be treated as an analog input. Any noise received on this circuitry
will result in corruption in the digitization process and lower
overall performance. The Encode clock must be isolated from
the digital outputs and the analog inputs.
Replacing the AD9432 with the AD9433
The AD9433 is pin-compatible with the AD9432, although
there are two control pins on the AD9433 that do not connect
(DNC) and supply (V
CC
) connections on the AD9432. They are
summarized in the table below.
Table IV. AD9432/AD9433 Pin Differences
Pin
AD9432
AD9433
41
42
DNC
V
CC
DFS
SFDR MODE
Using the AD9433 in an AD9432 pin assignment will configure
the AD9433 as follows:
The SFDR improvement circuit will be enabled.
The DFS pin will float LOW, selecting two
’
s complement
coding for the digital outputs, which is the same as the AD9432.
Table V summarizes differences between the AD9432 and
AD9433 analog and encode input common-mode voltages.
These inputs may be ac-coupled so that the devices can be used
interchangeably.
Table V. Other AD9432/AD9433 Differences
Attribute
AD9432
AD9433
ENCODE/
ENCODE
V
COMMON MODE
AIN/
AIN
V
COMMON MODE
1.6 V
3.0 V
3.75 V
4.0 V
Digital Outputs
The digital outputs are 3 V (2.7 V to 3.3 V) TTL/CMOS-
compatible for lower power consumption. The output data
format is selectable through the data format select (DFS)
CMOS input. DFS = 1 selects offset binary; DFS = 0 selects
two
’
s complement coding.
Table II. Offset Binary Output Coding (DFS = 1, V
REF
= 2.5 V)
AIN –
AIN
(V)
Range = 2 V p-p
Digital
Output
Code
4095
+1.000
1111 1111 1111
G
G
G
G
2048
2047
G
0
–
0.00049
G
1000 0000 0000
0111 1111 1111
G
G
G
G
0
G
–
1.000
G
0000 0000 0000
Table III. Two’s Complement Output Coding (DFS = 0, V
REF
= 2.5 V)
AIN –
AIN
(V)
Range = 2 V p-p
Digital
Output
Code
+2047
+1.000
0111 1111 1111
G
G
G
G
0
–
1
G
0
–
0.00049
G
0000 0000 0000
1111 1111 1111
G
G
G
G
–
2048
G
–
1.000
G
1000 0000 0000
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9433 (VREFOUT). In normal operation the internal reference
is used by strapping Pin 45 to Pin 46 and placing a 0.1 F
decoupling capacitor at VREFIN. The input range can be
adjusted by varying the reference voltage applied to the
AD9433. No appreciable degradation in performance occurs
when the reference is adjusted to 50. The full-scale range of the
ADC tracks reference voltage changes linearly.
Timing
The AD9433 provides latched data outputs, with 10 pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (see Timing Dia-
gram). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the AD9433
;
these transients can detract from the converter
’
s dynamic per-
formance. The minimum guaranteed conversion rate of the
AD9433 is 10 MSPS. At internal clock rates below 10 MSPS,
dynamic performance may degrade.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9433BSQ-105 | 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9444BSVZ-80 | 14-Bit, 80 MSPS, A/D Converter |
| AD9444 | 14-Bit, 80 MSPS, A/D Converter |
| AD9445-IF-PCB | 14-Bit, 105/125 MSPS, IF Sampling ADC |
| AD9445BSVZ-105 | 14-Bit, 105/125 MSPS, IF Sampling ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9433/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter |
| AD9433BSQ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 105 MSPS ADC - Bulk |
| AD9433BSQ-125 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 125Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 125 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD9433BSQZ-105 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP |
| AD9433BSQZ-125 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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