參數(shù)資料
型號(hào)： AD9433
廠(chǎng)商： Analog Devices, Inc.
英文描述： 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter
中文描述： 12位，105 MSPS/125 MSPS的中頻采樣的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 1001K
代理商： AD9433
REV. 0
AD9433
–14–
Shown in Figure 9 is another preferred method for clocking the
AD9433. The clock source (low jitter) is converted from single-
ended to differential using an RF transformer. The back-to-back
Schottky diodes across the transformer secondary limit clock
excursions into the AD9433 to approximately 0.8 V p-p differ-
ential. This helps prevent the large voltage swings of the clock
from feeding through to the other portions of the AD9433, and
limits the noise presented to the ENCODE inputs. A crystal
clock oscillator can also be used to drive the RF transformer if
an appropriate limiting resistor (typically 100
) is placed in the
series with the primary.
ENCODE
ENCODE
AD9433
CLOCK
SOURCE
0.1 F
100
HMS2812
DIODES
T1
–
4T
Figure 9. Transformer-Coupled Encode Circuit
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and
ENCODE
in single-ended and differential mode are shown
in Figure 10.
Table I. ENCODE Inputs
Description
Minimum Nominal Maximum
Differential Signal Amplitude 200 mV
(V
ID
)
Input Voltage Range
(V
IHD
, V
ILD
, V
IHS
, V
ILS
)
Internal Common-Mode Bias
(V
ICM
)
External Common-Mode Bias 2.0 V
(V
ECM
)
750 mV
5.5 V
–
0.5 V
V
CC
+ 0.5 V
3.750 V
4.25 V
V
IHS
V
ILS
0.1 F
V
IHD
V
ICM
,
V
ECM
V
ILD
ENCODE
ENCODE
ENCODE
ENCODE
V
ICM
,
V
ECM
Figure 10. Differential and Single-Ended Input Levels
Analog Input
The analog input to the AD9433 is a differential buffer.
The input buffer is self-biased by an on-chip resistor divider
that nominally sets the dc common-mode voltage to 4 V (see
Equivalent Circuits section). Rated performance is achieved
by driving the input differentially. Minimum input offset voltage
is
obtained
when driving from a source with a low differential
source impedance, such as a transformer, in ac applica-
tions
(See Figure 11)
. Capacitive coupling at the inputs will
increase the input offset voltage by as much as 50 mV.
50
ANALOG
SIGNAL
SOURCE
1:1
25
25
AIN
AIN
0.1 F
Figure 11. Transformer-Coupled Analog Input Circuit
In the highest frequency applications, two transformers con-
nected in series may be necessary to minimize even-order
harmonic distortion. The first transformer will isolate and con-
vert the signal to a differential signal, but the grounded input on
the primary side will degrade amplitude balance on the second-
ary winding. Capacitive coupling between the windings causes
this imbalance. Since one input to the first transformer is
grounded, there is little or no capacitive coupling, resulting in an
amplitude mismatch at the first transformers output. A second
transformer will improve the amplitude balance, and thus
improve the harmonic distortion. A wideband transformer, such
as the ADT1-1WT from Mini Circuits, is recommended for
these applications, as the bandwidth through the two transformers
will be reduced by the
√
2
.
50
ANALOG
SIGNAL
SOURCE
1:1
25
25
AIN
AIN
0.1 F
1:1
AD9433
Figure 12. Driving the Analog Input with Two Transformers
for Improved Even-Order Harmonics
Driving the ADC single-endedly will degrade performance,
particularly even-order harmonics. For best dynamic performance,
impedances at AIN and
AIN
should match.
Special care was taken in the design of the analog input section
of the AD9433 to prevent damage and corruption of data when
the input is overdriven.
SFDR Optimization
The SFDR MODE pin enables (SFDR MODE = 1) a propri-
etary circuit that may improve the spurious free dynamic range
(SFDR) performance of the AD9433. It is useful in applications
where the dynamic range of the system is limited by discrete
spurious frequency content caused by nonlinearities in the ADC
transfer function.
Enabling this circuit will give the circuit a dynamic transfer
function, meaning that the voltage threshold between two
adjacent output codes may change from clock cycle to clock
cycle. While improving spurious frequency content, this
dynamic aspect of the transfer function may be inappropriate
for some time domain applications of the converter. Connecting
the SFDR MODE pin to ground will disable this function. The
typical performance curves section of the data sheet illustrates
the improvement in the linearity of the converter and its effect
on spurious free dynamic range (TPC 1, 2, 15, 18).
相關(guān)PDF資料
PDF描述
AD9433BSQ-105 12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter
AD9444BSVZ-80 14-Bit, 80 MSPS, A/D Converter
AD9444 14-Bit, 80 MSPS, A/D Converter
AD9445-IF-PCB 14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445BSVZ-105 14-Bit, 105/125 MSPS, IF Sampling ADC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9433/PCB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter
AD9433BSQ-105 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 105 MSPS ADC - Bulk
AD9433BSQ-125 制造商:Analog Devices 功能描述:ADC Single Pipelined 125Msps 12-bit Parallel 52-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 125 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi
AD9433BSQZ-105 制造商:Analog Devices 功能描述:ADC Single Pipelined 105Msps 12-bit Parallel 52-Pin LQFP
AD9433BSQZ-125 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
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