參數(shù)資料
型號: AD9410
廠商: Analog Devices, Inc.
英文描述: 10-Bit, 210 MSPS A/D Converter
中文描述: 10位,210 MSPS的A / D轉(zhuǎn)換
文件頁數(shù): 6/20頁
文件大?。?/td> 315K
代理商: AD9410
REV. 0
AD9410
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24,
27, 28, 29, 30, 71, 72, 73, 74, 77, 78
3, 7, 14, 15
4
5
6
10
11
18
19
22
23
AGND
Analog Ground.
V
CC
REF
OUT
REF
IN
DNC
A
IN
A
IN
ENCODE
ENCODE
DS
DS
5 V Supply. (Regulate to within
±
5%.)
Internal Reference Output.
Internal Reference Input.
Do Not Connect.
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Data Sync (Input)—True. Tie LOW if not used.
Data Sync (Input)—Complement. Float and decouple with 0.1
μ
F
capacitor if not used.
3.3 V Analog Supply. (Regulate to within
±
5%.)
Digital Ground.
3.3 V Digital Output Supply. (2.5 V to 3.6 V)
Digital Data Output for Channel B. (LSB = D
B0
.)
Digital Data Output for Channel B. (MSB = D
B9
.)
Data Overrange for Channel B.
Clock Output—Complement.
Clock Output—True.
Digital Data Output for Channel A. (LSB = D
A0
.)
Digital Data Output for Channel A. (MSB = D
A9
.)
Data Overrange for Channel A.
Data Format Select. HIGH = Two’s Complement, LOW = Binary.
Interleaved or Parallel Output Mode. Low = Parallel Mode, High =
Interleaved Mode. If tying high, use a current limiting series resistor
(2.5 k
) to the 5 V supply.
25, 26, 31, 32, 69, 70, 75, 76
33, 40, 49, 52, 59, 68
34, 41, 48, 53, 60, 67
35–39
42–46
47
50
51
54–58
61–65
66
79
80
V
D
DGND
V
DD
D
B0
–D
B4
D
B5
–D
B9
OR
B
DCO
DCO
D
A0
–D
A4
D
A5
–D
A9
OR
A
DFS
I/P
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