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參數(shù)資料
型號(hào): AD9398/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 34/44頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9398
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,視頻處理
已用 IC / 零件: AD9398
已供物品:
相關(guān)產(chǎn)品: AD9398KSTZ-100-ND - IC INTERFACE 100MHZ HDMI 100LQFP
AD9398KSTZ-150-ND - IC INTERFACE 150MHZ HDMI 100LQFP
AD9398
Rev. 0 | Page 4 of 44
AD9398KSTZ-100
AD9398KSTZ-150
Parameter
Test Level
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
POWER SUPPLY
VD Supply Voltage
IV
3.15
3.3
3.47
3.15
3.3
3.47
V
VDD Supply Voltage
IV
1.7
3.3
347
1.7
3.3
347
V
DVDD Supply Voltage
IV
1.7
1.8
1.9
1.7
1.8
1.9
V
PVDD Supply Voltage
IV
1.7
1.8
1.9
1.7
1.8
1.9
V
V
80
100
80
110
mA
V
40
1003
55
1751
mA
V
88
110
145
mA
IPVDD Supply Current (Typical Pattern)
V
26
35
30
40
mA
Power-Down Supply Current (IPD)
VI
130
mA
AC SPECIFICATIONS
Intrapair (+ to ) Differential Input
Skew (TDPS)
IV
360
ps
Channel to Channel Differential Input
Skew (TCCS)
IV
6
Clock
period
Low-to-High Transition Time for Data
and Controls (DLHT)
IV
Output drive = high;
CL = 10 pF
900
ps
IV
Output drive = low;
CL = 5 pF
1300
ps
Low-to-High Transition Time for
DATACK (DLHT)
IV
Output drive = high;
CL = 10 pF
650
ps
IV
Output drive = low;
CL = 5 pF
1200
ps
High-to-Low Transition Time for Data
and Controls (DHLT)
IV
Output drive = high;
CL = 10 pF
850
ps
IV
Output drive = low;
CL = 5 pF
1250
ps
High-to-Low Transition Time for
DATACK (DHLT)
IV
Output drive = high;
CL = 10 pF
800
ps
IV
Output drive = low;
CL = 5 pF
1200
ps
Clock-to-Data Skew5 (TSKEW)
IV
0.5
2.0
0.5
2.0
ns
Duty Cycle, DATACK
IV
45
50
55
%
DATACK Frequency (FCIP)
VI
20
150
MHz
1 The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.
2 The typical pattern contains a gray scale area, output drive = high.
3 Specified current and power values with a worst-case pattern (on/off).
4 DATACK load = 10 pF, data load = 5 pF.
5 Drive strength = high.
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