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| 型號： | AD9398/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9398 |
| 標準包裝： | 1 |
| 主要目的： | 視頻，視頻處理 |
| 已用 IC / 零件： | AD9398 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9398KSTZ-100-ND - IC INTERFACE 100MHZ HDMI 100LQFP AD9398KSTZ-150-ND - IC INTERFACE 150MHZ HDMI 100LQFP |
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AD9398
Rev. 0 | Page 38 of 44
PCB LAYOUT RECOMMENDATIONS
The AD9398 is a high precision, high speed digital device. To
achieve the maximum performance from the part, it is impor-
tant to have a well designed board. The following is a guide for
designing a board using the AD9398.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is in the case where two or more
supply pins are adjacent to each other. For these groupings of
powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9398, since that interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads down to the power
plane is generally the best approach.
It is particularly important to maintain low noise and good
stability of PVDD (the clock generator supply). Abrupt changes
in PVDD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog
circuitry groups (VD and PVDD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during HSYNC and VSYNC periods). This can result in a
measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
analog supply voltage. This is mitigated by regulating the analog
supply, or at least PVDD, from a different, cleaner power source
(for example, from a 12 V supply).
It is recommended to use a single ground plane for the entire
board. Experience has repeatedly shown that noise performance
is the same or better with a single ground plane. Using multiple
ground planes is detrimental because each separate ground
plane is smaller, resulting in long ground loops.
In some cases, using separate ground planes is unavoidable;
therefore, it is recommended to place a single ground plane
under the AD9398. The location of the split should be at the
receiver of the digital outputs. In this case, it is even more
important to place components wisely because the current
loops are much longer (current takes the path of least
resistance). An example of a current loop is: power plane to
AD9398 to digital output trace to digital data receiver to digital
ground plane to analog ground plane .
OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance requiring more
current that causes more internal digital noise.
Shorter traces reduce the possibility of reflections.
Adding a 50 Ω to 200 Ω series resistor suppresses reflections,
reduces EMI, and reduces the current spikes inside the AD9398.
If series resistors are used, place them as close as possible to the
AD9398 pins (although try not to add vias or extra length to the
output trace to move the resistors closer).
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This is easily accomplished by keeping
traces short and connecting the outputs to only one device.
Loading the outputs with excessive capacitance increases the
current transients inside the AD9398 and creates more digital
noise on its power supplies.
DIGITAL INPUTS
The digital inputs on the AD9398 are designed to work with
3.3 V signals, but tolerate 5.0 V signals. Therefore, no extra
components need to be added if using 5.0 V logic.
Any noise that enters the HSYNC input trace adds jitter to the
system. Therefore, minimize the trace length and do not run
any digital or other high frequency traces near it.
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