參數(shù)資料
型號(hào)： AD9393BBCZ-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 80MHZ HDMI 76CSPBGA
標(biāo)準(zhǔn)包裝： 1
應(yīng)用： 視頻
接口： HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 76-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 76-CSPBGA（6x6）
包裝： 托盤(pán)
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
AD9393
Rev. 0 | Page 26 of 40
0x39—Bits[4:0], CSC_COEFF_A3 MSB and 0x3A—
Bits[7:0], CSC_COEFF_A3 LSB
The default value for the 13-bit A3 is 0x00000.
0x3B—Bits[4:0], CSC_COEFF_A4 MSB and 0x3C—
Bits[7:0], CSC_COEFF_A4 LSB
The default value for the 13-bit A4 is 0x19D7.
0x3D—Bits[4:0], CSC_COEFF_B1 MSB and 0x3E—
Bits[7:0], CSC_COEFF_B1 LSB
The default value for the 13-bit B1 is 0x1C54.
0x3F—Bits[4:0], CSC_COEFF_B2 MSB and 0x40—
Bits[7:0], CSC_COEFF_B2 LSB
The default value for the 13-bit B2 is 0x0800.
0x41—Bits[4:0], CSC_COEFF_B3 MSB and 0x42—
Bits[7:0], CSC_COEFF_B3 LSB
The default value for the 13-bit B3 is 0x1E89.
0x43—Bits[4:0], CSC_COEFF_B4 MSB and 0x44—
Bits[7:0], CSC_COEFF_B4 LSB
The default value for the 13-bit B4 is 0x0291.
0x45—Bits[4:0], CSC_COEFF_C1 MSB and 0x46—
Bits[7:0], CSC_COEFF_C1 LSB
The default value for the 13-bit C1 is 0x0000.
0x47—Bits[4:0], CSC_COEFF_C2 MSB and 0x48—
Bits[7:0], CSC_COEFF_C2 LSB
The default value for the 13 bit C2 is 0x0800.
0x49—Bits[4:0], CSC_COEFF_C3 MSB and 0x4A—
Bits[7:0], CSC_COEFF_C3 LSB
The default value for the 13-bit C3 is 0x0E87.
0x4B—Bits[4:0], CSC_COEFF_C4 MSB and 0x4C—
Bits[7:0], CSC_COEFF_C4 LSB
The default value for the 13-bit C4 is 0x18BD.
0x58—Bit[7], MCLK PLL Enable
This bit enables the use of the analog PLL.
0x58—Bits[6:4], MCLK PLL_N
These bits control the division of the MCLK out of the PLL. See
Table 16.
MCLK PLL_N [2:0]
MCLK Divide Value
0
/1
1
/2
2
/3
3
/4
4
/5
5
/6
6
/7
7
/8
0x58—Bit[3], N_CTS_Disable
This bit prevents the N/CTS packet on the link from writing to
the N and CTS registers.
0x58—Bits[2:0], MCLK FS_N
These bits control the multiple of 128 fS used for MCLK out. See
Table 17.
MCLK FS_N [2:0]
fS Multiple
0
128
1
256
2
384
3
512
4
640
5
768
6
896
7
1024
0x59—Bit[6], MDA/MCL PU
This bit disables the MDA/MCL pull-ups.
0x59—Bit[5], CLK Term O/R
This bit allows for overriding during power-down.
0 = auto, 1 = manual.
0x59—Bit[4], Manual CLK Term
This bit allows normal clock termination or disconnects this.
0 = normal, 1 = disconnected.
0x59—Bit[2], FIFO Reset UF
This bit resets the audio FIFO if underflow is detected.
0x59—Bit[1], FIFO Reset OF
This bit resets the audio FIFO if overflow is detected.
0x59—Bit[0], MDA/MCL Three-State
This bit three-states the MDA/MCL lines to allow in-circuit
programming of the EEPROM.
0x5A—Bits[6:0], Packet Detected
This register indicates if a data packet in specific sections has
been detected. These seven bits are updated if any specific
packet has been received since the last reset or loss of clock
detect. The default setting is 0x00. See Table 18.
Table 18.
Packet Detect Bit
Packet Detected
0
AVI infoframe
1
Audio infoframe
2
SPD infoframe
3
MPEG source infoframe
4
ACP packets
5
ISRC1 packets
6
ISRC2 packets
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