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參數(shù)資料
| 型號(hào)： | AD9289BBC-65EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 四8位，65 MSPS的串行LVDS 3V的A / D轉(zhuǎn)換 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 1376K |
| 代理商： | AD9289BBC-65EB |
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Prelimnary Technical Data
AD9289
Parameter
Rev. PrJ | Page 5 of 16
6/25/2004
Temp
Test
Level
Min
Typ
Max
Unit
f
IN1
= 19 MHz, f
IN2
= 20 MHz
f
IN1
= xx MHz, f
IN2
= xx MHz
25
°
C
25
°
C
V
V
dBc
dBc
TWO TONE
INTERMOD
DISTORTION (IMD)
Table 3: AC Specifications
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V; DIFFERENTIAL ENCODE INPUT
Parameter
Temp
Test Level
Min
Typ
Max
Unit
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
EH
)
Clock Pulse Width Low (t
EL
)
Valid Time (t
V
)
1
Propagation Delay (t
PD
)
1
MSB Propagation Delay (t
MSB
)
1
Rise Time (t
R
) (20% to 80%)
Fall Time (t
F
) (20% to 80%)
DCO Propagation Delay (t
CPD
)
Data to DCO Skew (t
PD
– t
CPD
)
Pipeline Latency
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25
°
C
25
°
C
VI
VI
IV
IV
VI
VI
VI
V
V
VI
IV
VI
V
V
65
6.9
6.9
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
pS
cycles
ps
ps rms
20
CLOCK
10
10
0.5
0.5
10
+/- 100
OUTPUT
PARAMETERS IN
LVDS MODE
6
<1
APERTURE
Table 4: Switching Specifications
EXPLANATION OF TEST LEVELS
TEST LEVEL
I
100% production tested.
II
100% production tested at +25
°
C and guaranteed by design and characterization at specified temperatures.
III
Sample Tested Only
IV
Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI
100% production tested at +25
°
C and guaranteed by design and characterization for industrial temperature range.
1
t
and t
are measured from the transition points of the CLK input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 5 pF or a dc current of ±40 μA. Rise and fall times measured from 20% to 80%.
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