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參數資料
| 型號： | AD9289BBC-65EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 四8位，65 MSPS的串行LVDS 3V的A / D轉換 |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 1376K |
| 代理商： | AD9289BBC-65EB |
Prelimnary Technical Data
AD9289
X
Rev. PrJ | Page 11 of 16
6/25/2004
Selected Mode
SENSE Voltage
Internal Switch Position
Resulting VREF (V)
Resulting Differential
Span (V p-p)
External Reference
AVDD
N/A
N/A
2 × External Reference
Internal
VREF
SENSE
0.5
1.0
Programmable
0.2 V to VREF
SENSE
0.5 × (1 + R2/R1)
2 × VREF
Internal
AGND to 0.2 V
Internal Divider
1.0
2.0
Table 1 Reference Settings
Digital Outputs
The AD9289’s differentialoutputs conform to the ANSI-644 LVDS
standard. To set the LVDS bias current, place a resistor (RSET is
nominally equal to 3.8 k
) to ground at the LVDSBIAS pin. The
RSET resistor current (~ 1.2/RSET) is ratioed on-chip setting the
output current at each output equal to a nominal 3.5 mA. A 100
differential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
The AD9289’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments. Single
point-to-point net topologies are recommended with a 100
termination resistor as close to the receiver as possible. It is
recommended to keep the trace length no longer than 3 inches and
to keep differential output trace lengths as equal as possible.
The format of the output data can be selected as offset binary or
twos complement. Pin S1 is used to set the format.
S1 Mode
Data Format
AVDD
Twos Complement
AGND
Offset Binary
Table 6: S1 Configuration
Timing
Data from each A/D is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 8-bits
times the sample clock rate, with a maximum of 520 MHz (8-bits x
65 MSPS = 520 MHz). The lowest typical conversion rate is 20
MSPS.
Two output clocks are provided to assist in capturing data from the
AD9289. The data clock out (DCO) is used to clock the output
data and is equal to four times the sampling clock (CLK) rate.
Data is clocked out of the AD9289 on the rising and falling edges
of DCO. The FCO clock is used to signal the start of a new output
byte and is equal to the sampling clock rate. See the Timing
Diagram for more information.
PLL LOCK Output
The AD9289 contains an internal PLL that is used to generate the
data clock out (DCO). When the PLL is locked, the LOCK/ signal
will be low, indicating valid data on the outputs.
If for any reason the PLL loses lock, the LOCK/ signal will go
high as soon as the lock circuitry detects an unlocked condition.
While the PLL is unlocked, the data outputs and DCO will remain
in the last known state. If the LOCK/ signal goes high in the
middle of a byte, no data or DCO signals will be available for the
rest of the byte. It will take at least 1
μ
s to regain lock if lock is
lost.
Once the PLL regains lock, the DCO will start. The first valid data
byte will be indicated by the FCO signal. See the Timing Diagram
for more information.
CML Pin
A common mode level output is available at F3. This output self-
biases to AVDD/2. This is a relatively high impedance output (two
5K resistors in series between AVDD and ground) with an output
impedance of 2.5K which may need to be considered when using
as a reference.
Overange
The AD9289 has an Overange output available that indicates when
the ADC is driven out of range. OR+ is driven high in overrange
condition, with the digital outputs are clamped to all zeroes or all
ones.Pin Function Descriptions
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