參數(shù)資料
型號(hào): AD9281-EB
廠(chǎng)商: Analog Devices, Inc.
英文描述: Dual Channel 8-Bit Resolution CMOS ADC
中文描述: 雙通道8位分辨率的CMOS模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù): 3/19頁(yè)
文件大?。?/td> 406K
代理商: AD9281-EB
–3–
REV. E
AD9281
Parameter
Symbol
Min
Typ
Max
Units
Condition
DYNAMIC PERFORMANCE (SE)
1
Signal-to-Noise and Distortion
f = 3.58 MHz
Signal-to-Noise
f = 3.58 MHz
Total Harmonic Distortion
f = 3.58 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
SINAD
47.2
dB
SNR
48
dB
THD
–55
dB
SFDR
–58
dB
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
DC Leakage Current
Input Capacitance
V
IH
V
IL
I
IN
C
IN
2.4
V
V
μ
A
pF
0.3
±
6
2
LOGIC OUTPUT (with DVDD = 3 V)
High Level Output Voltage
(I
OH
= 50
μ
A)
Low Level Output Voltage
(I
OL
= 1.5 mA)
V
OH
2.88
V
V
OL
0.095
V
LOGIC OUTPUT (with DVDD = 5 V)
High Level Output Voltage
(I
OH
= 50
μ
A)
Low Level Output Voltage
(I
OL
= 1.5 mA)
Data Valid Delay
MUX Select Delay
Data Enable Delay
V
OH
4.5
V
V
OL
t
OD
t
MD
t
ED
0.4
11
7
13
V
ns
ns
ns
C
L
= 20 pF. Output Level to
90% of Final Value
Data High-Z Delay
t
DHZ
13
ns
CLOCKING
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
t
CH
t
CL
16.9
16.9
ns
ns
Cycles
3.0
NOTES
1
SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.
2
AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.
3
IMD referred to larger of two input signals.
Specifications subject to change without notice.
CLOCK
INPUT
SELECT
INPUT
DATA
OUTPUT
ADC SAMPLE
#2
ADC SAMPLE
#3
ADC SAMPLE
#4
ADC SAMPLE
#5
Q CHANNEL
OUTPUT ENABLED
I CHANNEL
OUTPUT ENABLED
SAMPLE #1-3
Q CHANNEL
OUTPUT
SAMPLE #1-2
Q CHANNEL
OUTPUT
SAMPLE #1-1
Q CHANNEL
OUTPUT
SAMPLE #1-1
I CHANNEL
OUTPUT
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #1
I CHANNEL
OUTPUT
SAMPLE #2
Q CHANNEL
OUTPUT
t
MD
t
OD
ADC SAMPLE
#1
Figure 1. ADC Timing
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