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參數(shù)資料
| 型號(hào)： | AD9267EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9267 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 640M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 2 ~ 3 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 416mW @ 640MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9267 |
| 已供物品： | 板 |
AD9267
Rev. 0 | Page 18 of 24
In normal operation mode, the analog input can toggle the
OR±x pin for a number of clock cycles as it approaches full
scale. The OR±x pin is a pulse-width modulated (PWM) signal;
therefore, as the analog input increases in amplitude, the
duration of OR±x pin toggling increases. Eventually, when the
OR±x pin is high for an extended period of time, the ADC
overloads; thus, there is little correspondence between analog
input and digital output. In this mode, the duration of the
OR±x pin can be used as a coarse indicator to the signal
amplitude at the input of the ADC. In data valid mode, the
OR±x pin remains high when there are no memory access
operations taking place, such as internal calibration or factory
memory transfer, and the inputs of the ADC are within the
operating range.
In either modes of operation, the AUTORST bit can be enabled
and this automatically resets the modulator in an overload
condition. Because the OR±x signal is a PWM signal and the
toggling of OR±x does not always indicate an overload
condition, the modulator only resets after 16 consecutive clock
cycles where OR±x remains high or if the loop filter becomes
saturated. The OR±x pin remains high until the automatic reset
has completed.
If the AD9267 is used in a system that incorporates automatic
gain control (AGC), the OR±x signals can be used to indicate
that the signal amplitude should be reduced. This may be
particularly effective for use in maximizing the signal dynamic
range if the signal includes high occurrence components that
occasionally exceed full scale by a small amount.
TIMING
The AD9267 provides latched data outputs with a latency of
seven clock cycles. The AD9267 also provides a data clock
output (DCO±) pin intended to assist in capturing the data in
an external register. The data outputs are valid on the rising
edge of DCO±, unless changed by setting Serial Register 0x16[7]
(see the Serial Port Interface (SPI) section). See Figure 2 for a
graphical timing description.
Table 12. OR±x Conditions
Reset State
AUTORST
OR_IND1
OR_IND2
Function
Normal Reset Off
0
If overrange: OR±x = 1, else OR±x = 0
Data Valid Reset Off
0
1
If memory access: OR±x = 0, else OR±x = 1
Normal Reset On
1
0
If overrange or reset: OR±x = 1, else OR±x = 0
Data Valid Reset On
1
If memory access, or reset: OR±x = 0, else OR±x = 1
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