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參數(shù)資料
| 型號： | AD9260 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| 中文描述： | 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 30/36頁 |
| 文件大?。?/td> | 572K |
| 代理商： | AD9260 |
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AD9260
–30–
REV. B
AD817R
C15
0.1 F
C17
10 F
R11
49.9
JP10
R12
15k
R13
10k
R3
15k
R4
10k
R10
1k
VCC2
U6
C14
0.1 F
R8
390
R9
1k
Q1
2N2222
C12
0.1 F
C13
10 F
+
2.5/3V
NC
VOUT
TRIM
NC
+VIN
TEMP
GNDS
AD780R
U5
C18
0.1 F
C19
0.1 F
VCC2
1
2
3
4
8
7
6
5
AGND
AGND
AGND
VREFEXT
1KPOT
1V
+
Figure 70. Evaluation Board External Reference Circuitry
Table IX. Evaluation Board Recommended Resistance Value
for External Bias Resistor
Resistor
Value
Clock Speed
(max)
Power
Consumption
2 k
4 k
8 k
16 k
20 MHz
10 MHz
5 MHz
2.5 MHz
585 mW
325 mW
200 mW
150 mW
Data Interfacing Controls:
The data interfacing controls
(RESETB, CSB, READ, DAV) are all accessible via SMA
connectors (J2
–
J5) as illustrated in Figure 71 within the data
interfacing control block. The RESETB, CSB and READ
connections are each supplied with two sets or resistor pin
cups to allow the user to pull-up or pull-down each signal to
a fixed state. R5, R6 and R30 will terminate to ground, while
R7, R28 and R29 terminate to DRVDD. The DAV and
OTR signals are also directly connected to the data output
connector P1. All interfacing controls are buffered through
the CMOS line driver 74HC541.
Buffered Output Data:
The twos complement output data
is buffered through two CMOS noninverting bus transceivers
(U2 and U3) and made available at pin connector P1 as
illustrated in Figure 71 within the data output block.
Jumper Controlled Reference Source:
The choice of
reference for the AD9260 can easily be varied between 1.0 V,
2.5 V or external, by using Jumpers JP5, JP6, JP7 and JP9 as
illustrated in Figure 71 within the reference configuration
block. To obtain the desired reference see Table X.
Table X. Evaluation Board Reference Pin Configuration
Reference
Voltage
Input Voltage
(pk-pk FS)
Connect Jumper
2.5 V
1.0 V
External
JP7
JP6
JP5, JP9 and JP10
4.0 V
1.6 V
4.0 V
The external reference circuitry, is illustrated in Figure 70. By
connecting or disconnecting JP10, the external reference can be
configured for either 1.0 V or 2.5 V. That is, by connecting JP10,
the external reference will be configured to provide a 2.5 V
reference. By leaving JP10 open, the external reference will be
configured to provide a 1.0 V reference.
Flexible DC or AC Coupled External Clock Inputs:
As
illustrated in Figure 71, the AD9260 Evaluation Board is
designed to allow the user the flexibility of selecting how to
connect the external clock source. It is also equipped with a
playpen area for experimenting with optional clock drivers or
crystals.
Selecting DC or AC Coupled External Clock:
DC Coupled
: To directly drive the clock externally via the
CLKIN connector, connect JP11 and disconnect JP12. Note:
50
terminated by R27.
AC Coupled
: To ac couple the external clock and level shift it
to midsupply, connect JP12 and disconnect JP11. Note: 50
terminated by R27.
Flexible Input Signal Configuration Circuitry:
The
AD9260 Evaluation Board
’
s Input Signal Configuration Block
is illustrated in Figure 72. It is comprised of an input signal
summing amplifier (U7), a variable input signal common-
mode generator (U10) and a pair of amplifiers (U8 and U9)
that configure the input into a differential signal and drive it,
through a pair of isolation resistors, into the input pins of
AD9260. The user can either input a signal or dual signal
into the evaluation board via the two SMA connectors (J6 and
J7) labeled IN-1 or IN-2.
The user should refer to the Driving the Input section of the data
sheet for a detailed explanation of how the inputs are to be driven
and what amplifier requirements are recommended.
Selecting Single or Dual Signal Input:
The input ampli-
fier (U7) can either be configured as a dual input signal
inverting summer or a single tone inverting buffer. This
flexibility will allow for slightly better noise performance in
the single tone mode due to the inherent noise gain differ-
ence in the two amplifier configurations. An optional feed-
back capacitor (C9) was added to allow the user additional
out-of band filtering of the input signal if needed.
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PDF描述 |
|---|---|
| AD9260AS | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260EB | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9280ARSRL | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
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| AD9280-EB | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260AS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 2.5Msps 16-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:16-BIT HIGH SPEED OVERSAMPLED ADC - Bulk 制造商:Analog Devices 功能描述:Analog-Digital Converter IC Number of Bi |
| AD9260ASRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 2.5Msps 16-bit Parallel 44-Pin MQFP T/R 制造商:Rochester Electronics LLC 功能描述:16-BIT HIGH SPEED OVERSAMPLED ADC - Bulk |
| AD9260ASZ | 功能描述:IC ADC CMOS 16BIT OVRSAMP 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9260ASZRL | 功能描述:IC ADC 16BIT 2.5MHZ 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9260EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
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