參數資料
型號: AD9260
廠商: Analog Devices, Inc.
英文描述: High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
中文描述: 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數轉換器
文件頁數: 26/36頁
文件大?。?/td> 572K
代理商: AD9260
AD9260
–26–
REV. B
interpreted in terms of a number of samples stored in the
decimation filter. For example, if the part is in 8
×
decimation
mode, the delay is 321/f
CLOCK
. This corresponds to 321 samples
stored in the decimation filter. These 321 samples must be
flushed from the AD9260 after
RESET
is pulsed high prior to
reusing the data from the AD9260. That is, the AD9260 should
be allowed to clock for 321 samples as the corrupted data is
flushed from the filters. If the part is in 4
×
or 2
×
decimation
mode, then the relatively smaller group delays of the 4
×
and 2
×
decimation filters result fewer samples that must be flushed
from the filters (108 samples and 23 samples respectively).
In 2
×
, 4
×
or 8
×
mode,
RESET
may be used to synchronize
multiple AD9260s clocked with the same clock. The decimation
filters in the AD9260 are clocked with an internal clock divider.
The state of this clock divider determines when the output data
becomes available (relative to CLK). In order to synchronize
multiple AD9260s clocked with the same clock, it is necessary
that the clock dividers in each of the individual AD9260s are
all reset to the same state. When
RESET
is asserted low, these
clock dividers are cleared. On the next falling edge of CLK follow-
ing the rising edge of
RESET,
the clock dividers begin counting
and the clock is applied to the digital decimation filters.
OTR PIN
The OTR pin is a synchronous output that is updated each
CLK period. It indicates that an overrange condition has oc-
curred within the AD9260. Ideally, OTR should be latched on
the falling edge of CLK to ensure proper setup-and-hold time.
However, since an overrange condition typically extends well
beyond one clock cycle (i.e., does not toggle at the CLK rate).
OTR typically remains high for more than a clock cycle, allow-
ing it to be successfully detected on the rising edge of CLK or
monitored asynchronously.
An overrange condition must be carefully handled because of
the group delays in the low-pass digital decimation filters in the
output stages of the AD9260. When the input signal exceeds
the full-scale range of the converter, this can have a variety of
effects upon the operation of the AD9260, depending on the
duration and amplitude of this overrange condition. A short
duration overrange condition (<< filter group delay) may cause
the analog modulator to briefly overrange without causing the
data in the low pass digital filters to exceed full scale. The ana-
log modulator is actually capable of processing signals slightly
(3%) beyond the full-scale range of the AD9260 without inter-
nally clipping. A long duration overrange condition will cause
the digital filter data to exceed full scale. For this reason, the
OTR signal is generated using two separate internal out-of-
range detectors.
The first of these out-of-range detectors is placed at the output
of the analog modulator and indicates whether the modulator
output signal has extended 3% beyond the full-scale range of
the converter. If the modulator output signal exceeds 3% be-
yond full scale, the digital data is hard-limited (i.e., clipped) to a
number that is 3% larger than full scale. Due to the delay of the
switched capacitor analog modulator, the OTR signal is delayed
3 1/2 clock cycles relative to the clock edge in which the over-
ranged analog input signal was sampled.
The second out-of-range detector is placed at the output of the
stage three decimation filter and detects whether the low pass
filtered data has exceeded full scale. When this occurs, the filter
output data is hard limited to full scale. The OTR signal is a
logical OR function of the signals from these two internal out-
of-range detectors. If either of these detectors produces an out-
of-range signal, the OTR pin goes high and the data may be
seriously corrupted.
If the AD9260 is used in a system that incorporates automatic
gain control (AGC), the OTR signal may be used to indicate
that the signal amplitude should be reduced. This may be par-
ticularly effective for use in maximizing the signal dynamic
range if the signal includes high-frequency components that
occasionally exceed full scale by a small amount. If, on the other
hand, the signal includes large amplitude low frequency compo-
nents that cause the digital filters to overrange, this may cause
the low pass digital filter to overrange. In this case the data may
become seriously corrupted and the digital filters may need to
be flushed. See the
RESET
pin function description above for
an explanation of the requirements for flushing the digital filters.
OTR should be sampled with the falling edge of CLK. This
signal is invalid while CLK is HIGH.
MODE OPERATION
The Mode Select Pin (MODE) allows the user to select one of
four available digital filter modes using a single pin. Each mode
configures the internal decimation filter to decimate at: 1
×
, 2
×
,
4
×
or 8
×
. Refer to Table VII for mode pin ranges.
The mode selection is performed by using a set of internal com-
parators, as illustrated in Figure 62, so that each mode corre-
sponds to a voltage range on the input of the MODE pin. The
output of the comparators are fed into encoding logic where, on
the falling edge of the clock, the encoded data is latched.
Table VII. Recommended Mode Pin Ranges and Configurations
Mode Pin
Range
Typical
Mode Pin
Decimation
Mode
0 V
0.5 V
0.5 V
1.5 V
1.5 V
3.0 V
3.0 V
5.0 V
GND
VREF/2
CML
AVDD
8
×
2
×
4
×
1
×
BIAS PIN OPERATION
The Bias Select Pin (BIAS) gives the user, who is able to oper-
ate the AD9260 at a slower clock rate, the added flexibility of
running the device in a lower, power consumption mode when it
is clocked at less than 20 MHz.
This is accomplished by scaling the bias current of the AD9260
as illustrated in Figure 63. The bias amplifier drives a source
follower and forces 1 V across R
EXT
, which sets the bias current.
This effectively adjusts the bias current in the modulator ampli-
fiers and FLASH preamplifiers. When a large value of R
EXT
is
used, a smaller bias current is available to the internal amplifier
circuitry. As a result these amplifiers need more time to settle,
thus dictating the use of a slower clock as the power is reduced.
Refer to the characterization curves shown in Figures 41
48
revealing the performance tradeoffs.
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