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參數(shù)資料
| 型號： | AD9245BCPRL7-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, 3 V A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | EXPOSED PAD, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 1510K |
| 代理商： | AD9245BCPRL7-80 |
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AD9245
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
—The analog
input frequency at which the spectral power of the fundamental
frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay (t
A
)
—The delay between the 50% point of the
rising edge of the clock and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter, t
J
)
—The sample-to-sample varia-
tion in aperture delay.
Integral Nonlinearity (INL
)—The deviation of each individual
code from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs LSB
before the first code transition. Positive full scale is defined as a
level 1 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Differential Nonlinearity (DNL, No Missing Codes)
—An
ideal ADC exhibits code transitions that are exactly 1 LSB apart.
DNL is the deviation from this ideal value. Guaranteed no miss-
ing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Offset Error
—The major carry transition should occur for an
analog value LSB below VIN+ = VIN–. Offset error is
defined as the deviation of the actual transition from that point.
Gain Error
—The first code transition should occur at an
analog value LSB above negative full scale. The last transition
should occur at an analog value 1 LSB below the positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Temperature Drift
—The temperature drift for offset error and
gain error specifies the maximum change from the initial
(25°C) value to the value at T
MIN
or T
MAX
.
Power Supply Rejection Ratio
—The change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)
1
—
The ratio of the rms
input signal amplitude to the rms value of the sum of the first
six harmonic components.
Signal-to-Noise and Distortion (SINAD)
1
—
The ratio of the
rms input signal amplitude to the rms value of the sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc.
Effective Number of Bits (
ENOB
)—
The effective number of
bits for a sine wave input at a given input frequency can be cal-
culated directly from its measured
SINAD
using the following
formula:
(
)
02
.
76
.
=
SINAD
ENOB
Signal-to-Noise Ratio (SNR)
1
—
The ratio of the rms input
signal amplitude to the rms value of the sum of all other spec-
tral components below the Nyquist frequency, excluding the
first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
1
—
The difference in dB
between the rms input signal amplitude and the peak spurious
signal. The peak spurious component may or may not be a
harmonic.
Two-Tone SFDR
1
—
The ratio of the rms value of either input
tone to the rms value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle
—Pulsewidth high is the
minimum amount of time that the clock pulse should be left in
the Logic 1 state to achieve rated performance. Pulsewidth low
is the minimum time the clock pulse should be left in the
Logic 0 state. At a given clock rate, these specifications define an
acceptable clock duty cycle.
Minimum Conversion Rate
—The clock rate at which the SNR
of the lowest analog signal frequency drops by no more than
3 dB below the guaranteed limit.
Maximum Conversion Rate
—The clock rate at which para-
metric testing is performed.
Output Propagation Delay (t
PD
)—
The delay between the clock
rising edge and the time when all bits are within valid logic
levels.
Out-of-Range Recovery Time
—The time it takes for the ADC
to reacquire the analog input after a transition from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
1
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. B | Page 8 of 28
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9245BCPZ-20 | 功能描述:IC ADC 14BIT SGL 20MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9245BCPZ-202 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| AD9245BCPZ-40 | 功能描述:IC ADC 14BIT SGL 40MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9245BCPZ-402 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| AD9245BCPZ-65 | 功能描述:IC ADC 14BIT SGL 65MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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