參數(shù)資料
型號(hào)： AD9244BSTRL-65
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 14-Bit, 40/65 MSPS Monolithic A/D Converter
中文描述： 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48
封裝： MS-026-BBC, LQFP-48
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 1845K
代理商： AD9244BSTRL-65
REV. A
–16–
AD9244
A differential input structure allows the user to easily configure
the inputs for either single-ended or differential operation. The
ADC
’
s input structure allows the dc offset of the input signal to
be varied independent of the input span of the converter. Specifi-
cally, the input to the ADC core can be defined as the difference
of the voltages applied at the
VIN+
and
VIN–
input pins.
Therefore, the equation
V
defines the output of the differential input stage and provides
the input to the ADC core. The voltage,
V
CORE
, must satisfy the
condition
–
where
VREF
is the voltage at the
VREF
pin.
In addition to the limitations placed on the input voltages
VIN
+
and
VIN
–
by Equations 1 and 2, boundaries on the inputs
also exist based on the power supply voltages according to the
conditions
VIN
VIN
CORE
=
+
–
–
(1)
/
/
VREF
V
VREF
CORE
2
2
<
<
(2)
AGND
V
VIN
AVDD
V
AGND
V
VIN
AVDD
V
–
.
0 3
.
–
.
0 3
–
.
0 3
0 3
<
+ <
+
<
<
+
(3)
where
AGND
is nominally 0 V and
AVDD
is nominally 5 V. The
range of valid inputs for
VIN+
and
VIN–
is any combination that
satisfies both Equations 2 and 3.
For additional information showing the relationship between
VIN+, VIN–, VREF,
and the analog input range of the AD9244,
see Tables I and II.
ANALOG INPUT OPERATION
Figure 5 shows the equivalent analog input of the AD9244,
which consists of a 750 MHz differential SHA. The differential
input structure of the SHA is flexible, allowing the device to be
configured for either a differential or single-ended input. The
analog inputs VIN+ and VIN
–
are interchangeable, with the
exception that reversing the inputs to the VIN+ and VIN
–
pins
results in a data inversion (complementing the output word).
S
S
VIN+
VIN–
C
PIN, PAR
S
S
H
+
–
C
S
C
S
C
H
C
H
C
PIN, PAR
Figure 5. Analog Input of AD9244 SHA
Table I. Analog Input Configuration Summary
Input
Connection
Single-Ended
Input
Span (V) VIN+
*
Input Range (V)
Input CM
Voltage
1.0
Coupling
DC or AC 1.0
VIN
–
*
1.0
Comments
Best for stepped input response applications.
0.5 to 1.5
2.0
1 to 3
2.0
2.0
Optimum noise performance for single-ended
mode, often requires low distortion op amp with
VCC > 5 V due to its headroom issues.
Differential
DC or AC 1.0
2.25 to 2.75 2.75 to 2.25 2.5
Optimum full-scale THD and SFDR performance
well beyond the ADC
’
s Nyquist frequency.
2.0
2.0 to 3.0
3.0 to 2.0
2.5
Optimum noise performance for differential mode
Preferred mode for applications.
*
VIN+ and VIN
–
can be interchanged if data inversion is required.
Table II. Reference Configuration Summary
Reference
Operating Mode
Internal
Internal
Internal
Input Span (VIN
+
–
VIN
–
)
(V p-p)
1
2
1 SPAN 2
(SPAN = VREF)
SPAN = EXTERNAL REF
Connect
SENSE
SENSE
R1
R2
SENSE
VREF
To
VREF
AGND
VREF and SENSE
SENSE and REFGND
AVDD
EXTERNAL REF
Resulting VREF (V)
1
2
1 VREF 2.0
VREF = (1 + R1/R2)
1 VREF 2.0
External
相關(guān)PDF資料
PDF描述
AD9244-EVAL 14-Bit, 40/65 MSPS Monolithic A/D Converter
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AD9245 14-Bit, 80 MSPS, 3 V A/D Converter
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