參數(shù)資料
型號(hào): AD9244BST-40
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 14-Bit, 40/65 MSPS Monolithic A/D Converter
中文描述: 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: MS-026-BBC, LQFP-48
文件頁數(shù): 5/36頁
文件大?。?/td> 1845K
代理商: AD9244BST-40
REV. A
AD9244
–5–
Test
Level
AD9244BST-65
Min
Typ
AD9244BST-40
Min
Typ
Parameter
Temp
Max
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
Clock Period
1
Clock Pulsewidth High
2
Clock Pulsewidth Low
2
Clock Pulsewidth High
3
Clock Pulsewidth Low
3
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
65
40
MHz
kHz
ns
ns
ns
ns
ns
500
500
15.4
4
4
6.9
6.9
25
4
4
11.3
11.3
DATA OUTPUT PARAMETERS
Output Delay (t
PD
)
4
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Output Enable Delay
Full
Full
Full
Full
Full
V
V
V
V
V
3.5
7
3.5
7
ns
Clock Cycles
ns
ps rms
ns
8
1.5
0.3
15
8
1.5
0.3
15
OUT-OF-RANGE RECOVERY TIME
Full
V
2
1
Clock Cycles
NOTES
1
The clock period may be extended to 2
μ
s with no degradation in specified performance at 25
°
C.
2
With duty cycle stabilizer enabled.
3
With duty cycle stabilizer disabled.
4
Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
Specifications subject to change without notice
(AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.)
SWITCHING SPECIFICATIONS
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
ANALOG
INPUT
CLOCK
DATA
OUT
t
PD
t
A
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
Figure 1. Input Timing
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