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參數(shù)資料
| 型號： | AD9244BST-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 40/65 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 1845K |
| 代理商： | AD9244BST-40 |
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REV. A
–20–
AD9244
Clock Input Considerations
The analog input is sampled on the rising edge of the clock.
Timing variations, or jitter, on this edge causes the sampled
input voltage to be in error by an amount proportional to the
slew rate of the input signal and to the amount of the timing
variation. Thus, to maintain the excellent high frequency SFDR
and SNR characteristics of the AD9244, it is essential that the
clock edge be kept as clean as possible.
The clock should be treated like an analog signal. Clock drivers
should not share supplies with digital logic or noisy circuits. The
clock traces should not run parallel to noisy traces. Using a pair
of symmetrically routed, differential clock signals can help to
provide immunity from common-mode noise coupled from the
environment.
The clock receiver functions like a differential comparator. At
the CLK inputs, a slowly changing clock signal will result in
more jitter than a rapidly changing one. Driving the clock with
a low amplitude sine wave input is not recommended. Running
a high speed clock through a divider circuit will provide a fast
rise/fall time, resulting in the lowest jitter in most systems.
CLK+
CLK–
AD9244
Figure 15a. Differential Clock Input—DC-Coupled
CLK+
CLK–
AD9244
AGND
0.1 F
1.6V
Figure 15b. Single-Ended Clock Input
—
DC-Coupled
CLK+
CLK–
AD9244
AGND
Figure 15c. Single-Ended Input
—
Retains Pin
Compatibility with AD9226
CLOCK OVERVIEW
The AD9244 has a flexible clock interface that accepts either a
single-ended or differential clock. An internal bias voltage facilitates
ac coupling using two external capacitors. To remain backward
compatible with the single-pin clock scheme of the AD9226, the
AD9244 can be operated with a dc-coupled, single-pin clock by
grounding the CLK
–
pin and driving CLK+.
When the CLK
–
pin is not grounded, the CLK+ and CLK
–
pins
function as a differential clock receiver. When CLK+ is greater
than CLK
–
, the SHA is in hold mode; when CLK+ is less than
CLK
–
, the SHA is in track mode (see timing in Figure 14). The
rising edge of the clock (CLK+
–
CLK
–
) switches the SHA from
track to hold and timing jitter on this transition should be mini-
mized, especially for high frequency analog inputs.
It is often difficult to maintain a 50% duty cycle to the ADC,
especially when driving the clock with a single-ended or sine
wave input. To ease the constraint of providing an accurate
50% clock, the ADC has an optional internal duty cycle stabilizer
(DCS) that allows the rising clock edge to pass through with
minimal jitter and interpolates the falling edge, independent of
the input clock falling edge. The DCS is described in greater
detail in a later section.
Clock Input Modes
Figures 15a to 15e illustrate the modes of operation of the clock
receiver. Figure 15a shows a differential clock directly coupled to
CLK+ and CLK
–
. In this mode, the common mode of the CLK+
and CLK
–
signals should be close to 1.6 V. Figure 15b illustrates
a single-ended clock input. The capacitor decouples the internal
bias voltage on the CLK
–
pin (about 1.6 V), establishing a threshold
for the CLK+ pin. Figure 15c provides backward compatibility
with the AD9226. In this mode, CLK
–
is grounded and the
threshold for CLK+ is 1.5 V. Figure 15d shows a differential clock
ac-coupled by connecting through two capacitors. AC coupling
a single-ended clock can also be accomplished using the circuit
in Figure 15e.
When using the differential clock circuits of Figure 15a or
Figure 15d, if CLK
–
drops below 250 mV, the mode of the clock
receiver may change, causing conversion errors. It is essential
that CLK
–
remain above 250 mV when the clock is ac-coupled
or dc-coupled.
CLK–
CLK+
CLK–
CLK+
SHA IN
HOLD
SHA IN
TRACK
Figure 14. SHA Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9244BST-40Z | 制造商:Analog Devices 功能描述:ADC 14BIT 40MSPS 1.3LSB 48 制造商:Analog Devices 功能描述:ADC, 14BIT, 40MSPS, 1.3LSB, 48LQFP; Resolution (Bits):14bit; Sampling Rate:40MSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:64mA; Digital IC Case Style:LQFP; No. of Pins:48; Input;RoHS Compliant: Yes |
| AD9244BST-65 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 65Msps 14-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14 BIT 40/65 MSPS IF SAMPLIGN ADC - Bulk 制造商:Analog Devices 功能描述:IC 14BIT ADC SMD 9244 LQFP48 制造商:Analog Devices 功能描述:ADC,AD9244B 14bit 65MSPS LQFP |
| AD9244BSTRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9244BSTRL-65 | 制造商:Analog Devices 功能描述:Single ADC Pipelined 65Msps 14-bit Parallel 48-Pin LQFP T/R |
| AD9244BSTZ40 | 制造商:Analog Devices 功能描述: |
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