參數(shù)資料
型號(hào)： AD9244-EVAL
廠商： Analog Devices, Inc.
英文描述： 14-Bit, 40/65 MSPS Monolithic A/D Converter
中文描述： 14位，六十五分之四十MSPS的單片機(jī)的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 21/36頁(yè)
文件大小： 1845K
代理商： AD9244-EVAL
REV. A
AD9244
–21–
speed. When the stabilizer is disabled, the internal switching will
be directly affected by the clock state. If CLK+ is high, the SHA
will be in hold mode; if CLK+ is low, the SHA will be in track
mode. TPC 16 shows the benefits of using the clock stabilizer.
Connecting the DCS pin to AVDD implements the internal clock
stabilization function in the AD9244. If the DCS pin is connected
to ground, the AD9244 will use both edges of the external clock
in its internal timing circuitry (see Specifications for timing
requirements).
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in high speed, high resolution sys-
tems. Multilayer printed circuit boards (PCBs) are recommended
to provide optimal grounding and power distribution. The use of
power and ground planes offers distinct advantages, including:
The minimization of the loop area encompassed by a signal
and its return path.
The minimization of the impedance associated with ground
and power paths.
The inherent distributed capacitor formed by the power
plane, PCB material, and ground plane.
It is important to design a layout that minimizes noise from
coupling onto the input signal. Digital input signals should not be
run in parallel with input signal traces and should be routed away
from the input circuitry. While the AD9244 features separate
analog and digital ground pins, it should be treated as an analog
component. The AGND and DGND pins must be joined together
directly under the AD9244. A solid ground plane under the
ADC is acceptable if the power and ground return currents are
carefully managed.
Analog Supply Decoupling
The AD9244 features separate analog and digital supply and
ground circuits, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD (analog power) should be
decoupled to AGND (analog ground). The AVDD and AGND
pins are adjacent to one another. Figure 17 shows the recom-
mended decoupling for each pair of analog supplies; 0.1
μ
F
ceramic chip and 10
μ
F tantalum capacitors should provide
adequately low impedance over a wide frequency range. The
decoupling capacitors (especially 0.1
μ
F) should be located as
close to the pins as possible.
AD9244
AGND
AVDD
10 F
0.1 F
*
*
LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS
+
Figure 17. Analog Supply Decoupling
Digital Supply Decoupling
The digital activity on the AD9244 falls into two categories:
correction logic and output drivers. The internal correction
logic draws relatively small surges of current, mainly during the
clock transitions. The output drivers draw large current impulses
when the output bits change state. The size and duration of
these currents are a function of the load on the output bits; large
capacitive loads should be avoided.
CLK+
CLK–
AD9244
100pF – 0.1 F
Figure 15d. Differential Clock Input
—
AC-Coupled
CLK+
CLK–
AD9244
AGND
0.1 F
0.1 F
1.6 V
Figure 15e. Single-Ended Clock Input
—
AC-Coupled
Clock Power Dissipation
Most of the power dissipated by the AD9244 is from the analog
power supplies. However, lower clock speeds will reduce digital
supply current. Figure 16 shows the relationship between power
and clock rate.
SAMPLE RATE – MHz
0
70
10
20
30
40
50
60
600
200
P
550
400
350
300
250
500
450
AD9244-40
AD9244-65
Figure 16. Power Consumption vs. Sample Rate
Clock Stabilizer (DCS)
The clock stabilizer circuit in the AD9244 desensitizes the ADC
from clock duty cycle variations. System clock constraints are
eased by internally restoring the clock duty cycle to 50%, inde-
pendent of the clock input duty cycle. Low jitter on the rising
edge (sampling edge) of the clock is preserved while the falling
edge is generated on-chip.
It may be desirable to disable the clock stabilizer and may be
necessary when the clock frequency is varied or completely stopped.
Note that stopping the clock is not recommended with ac-coupled
clocks. Once the clock frequency is changed, over 100 clock cycles
may be required for the clock stabilizer to settle to the new
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