參數(shù)資料
型號： AD9233BCPZRL7-105
廠商： Analog Devices Inc
文件頁數(shù)： 13/44頁
文件大小： 0K
描述： IC ADC 12BIT 105MSPS 48-LFCSP
標準包裝： 750
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 350mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應商設備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個單端，單極；1 個差分，單極
配用： AD9233-125EBZ-ND - BOARD EVALUATION FOR AD9233
AD9233
Rev. A | Page 20 of 44
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9233. Power
supplies for clock drivers should be separated from the ADC
output driver supplies to avoid modulating the clock signal with
digital noise. The power supplies should also not be shared with
analog input circuits such as buffers to avoid the clock
modulating onto the input signal or vice versa. Low jitter,
crystal-controlled oscillators make the best clock sources.
If the clock is generated from another type of source (by
gating, dividing, or other methods), it should be retimed by the
original clock at the last step.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance, and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter for more in-depth
information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 52 and Figure 53, the power dissipated by
the AD9233 is proportional to its sample rate. The digital power
dissipation is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current (IDRVDD) can be calculated as
N
f
C
V
I
CLK
LOAD
DRVDD
×
=
2
where N is the number of output bits (12 in the case of the
AD9233).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption.
The data used for Figure 52 and Figure 53 is based on the
same operating conditions as used in the plots in the Typical
Performance Characteristics section with a 5 pF load on each
output driver.
475
325
0
125
CLOCK FREQUENCY (MSPS)
P
O
WE
R
(
m
W)
450
425
400
375
350
250
0
CU
RRE
NT
(
m
A)
200
150
100
50
25
50
75
100
IDRVDD
IAVDD
TOTAL POWER
05
49
2-
03
4
Figure 52. AD9233-125 Power and Current vs. Clock Frequency, FIN = 30 MHz
410
250
5
CLOCK FREQUENCY (MSPS)
PO
W
E
R
(mW
)
200
180
0
CURR
E
NT
(
m
A)
160
140
120
100
80
60
40
20
30
55
80
105
390
370
350
330
310
290
270
IDRVDD
IAVDD
TOTAL POWER
0
549
2-
0
82
Figure 53. AD9233-105 Power and Current vs. Clock Frequency, FIN = 30 MHz
290
215
0
CLOCK FREQUENCY (MSPS)
P
O
WE
R
(
m
W)
150
0
CU
RRE
NT
(
m
A)
120
90
60
30
80
IDRVDD
IAVDD
TOTAL POWER
05
49
2-
0
93
275
260
245
230
20
40
60
Figure 54. AD9233-80 Power and Current vs. Clock Frequency, FIN = 30 MHz
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