參數(shù)資料
型號(hào)： AD9215BRUZRL7-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 80MSPS 3V 28TSSOP
設(shè)計(jì)資源： Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Interfacing the High Frequency AD8331 to AD9215 (CN0096)
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 10
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 104mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
配用： AD9215BCP-80EBZ-ND - BOARD EVAL FOR AD9215BCP-80
AD9215BCP-65EBZ-ND - BOARD EVAL FOR AD9215BCP-65
AD9215BCP-105EBZ-ND - BOARD EVAL FOR AD9215BCP-105
Data Sheet
AD9215
Rev. B | Page 3 of 36
SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise
noted.
Table 1. DC Specifications
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Parameter
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
VI
10
Bits
ACCURACY
No Missing Codes
Full
VI
Guaranteed
Offset Error1
Full
VI
±0.3
±2.0
±0.3
±2.0
±0.3
±2.0
% FSR
Gain Error1
Full
VI
0
+1.5
+4.0
+1.5
+4.0
+1.5
+4.0
% FSR
Differential Nonlinearity (DNL)2
Full
VI
1.0
±0.5
+1.0
1.0
±0.5
+1.0
1.0
±0.6
+1.2
LSB
Integral Nonlinearity (INL)2
Full
VI
±0.5
±1.2
±0.5
±1.2
±0.65
±1.2
LSB
TEMPERATURE DRIFT
Offset Error1
Full
V
+15
ppm/°C
Gain Error1
Full
V
+30
ppm/°C
Reference Voltage (1 V Mode)
Full
V
±230
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
VI
±2
±35
±2
±35
±2
±35
mV
Load Regulation @ 1.0 mA
Full
V
0.2
mV
Output Voltage Error (0.5 V Mode)
Full
V
± 1
±1
mV
Load Regulation @ 0.5 mA
Full
V
0.2
mV
INPUT REFERRED NOISE
VREF = 0.5 V
25°C
V
0.8
LSB rms
VREF = 1.0 V
25°C
V
0.4
LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V
Full
IV
1
V p-p
Input Span, VREF = 1.0 V
Full
IV
2
V p-p
Input Capacitance3
Full
V
2
pF
REFERENCE INPUT RESISTANCE
Full
V
7
k
POWER SUPPLIES
Supply Voltage
AVDD
Full
IV
2.7
3.0
3.3
2.7
3.0
3.3
2.7
3.0
3.3
V
DRVDD
Full
IV
2.25
2.5
3.6
2.25
2.5
3.6
2.25
2.5
3.6
V
Supply Current
IAVDD2
Full
VI
32
35
34.5
39
40
44
mA
IDRVDD2
25°C
V
7.0
8.6
11.3
mA
PSRR
Full
V
± 0.1
% FSR
POWER CONSUMPTION
Sine Wave Input2
IAVDD2
Full
VI
96
104
120
mW
IDRVDD2
25°C
V
18
20
25
mW
Standby Power4
25°C
V
1.0
mW
1
With a 1.0 V internal reference.
2
Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
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